cpu/amd/pi: Use AMD common block for TSC#887
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SergiiDmytruk
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May 13, 2026
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@SergiiDmytruk seems I have found the culprit: #889 |
Select options to utilize common AMD block for TSC. The coreboot timestamp table needs the tick frequency to be provided by TSC. Currently AMD PI CPU uses LAPIC as the timer, which does not provide the TSC tick frequency. It is also required to properly measure firmware performance in EDK2. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Select options to utilize common AMD block for TSC. The coreboot timestamp table needs the tick frequency to be provided by TSC. Currently AMD PI CPU uses LAPIC as the timer, which does not provide the TSC tick frequency. It is also required to properly measure firmware performance in EDK2.
Upstream-Status: Pending