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Add multiple TTL and CMOS subcircuits to eSim library #446

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54c98eb
feat: add 74HC107 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
ba0fc20
feat: add 74HC123 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
c862a9a
feat: add 74HC164 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
c4a30de
feat: add 74HC174 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
0e35ea9
feat: add 74HC273 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
e51ab30
feat: add 74HC393 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
030d2fa
feat: add 74HC4049 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
3816583
feat: add 74HC85 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
f805091
feat: add CD520b subcircuit to eSim library
Pavan-1611 Jan 29, 2026
016ba35
feat: add LS90 subcircuit to eSim library
Pavan-1611 Jan 29, 2026
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13 changes: 13 additions & 0 deletions library/SubcircuitLibrary/74HC107/74HC107.cir
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* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC107\74HC107.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/25 18:06:53

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U2 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad12_ Net-_U1-Pad7_ Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U1-Pad2_ d_jkff
U3 Net-_U1-Pad8_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad10_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_jkff
U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT

.end
20 changes: 20 additions & 0 deletions library/SubcircuitLibrary/74HC107/74HC107.cir.out
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* c:\fossee\esim\library\subcircuitlibrary\74hc107\74hc107.cir

* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ d_jkff
* u3 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ d_jkff
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
a1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ u2
a2 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ u3
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
73 changes: 73 additions & 0 deletions library/SubcircuitLibrary/74HC107/74HC107.pro
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=adc-dac
LibName2=memory
LibName3=xilinx
LibName4=microcontrollers
LibName5=dsp
LibName6=microchip
LibName7=analog_switches
LibName8=motorola
LibName9=texas
LibName10=intel
LibName11=audio
LibName12=interface
LibName13=digital-audio
LibName14=philips
LibName15=display
LibName16=cypress
LibName17=siliconi
LibName18=opto
LibName19=atmel
LibName20=contrib
LibName21=power
LibName22=eSim_Plot
LibName23=transistors
LibName24=conn
LibName25=eSim_User
LibName26=regul
LibName27=74xx
LibName28=cmos4000
LibName29=eSim_Analog
LibName30=eSim_Devices
LibName31=eSim_Digital
LibName32=eSim_Hybrid
LibName33=eSim_Miscellaneous
LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
LibName37=eSim_Nghdl
LibName38=eSim_Ngveri
LibName39=eSim_SKY130
LibName40=eSim_SKY130_Subckts
14 changes: 14 additions & 0 deletions library/SubcircuitLibrary/74HC107/74HC107.sub
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* Subcircuit 74HC107
.subckt 74HC107 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
* c:\fossee\esim\library\subcircuitlibrary\74hc107\74hc107.cir
* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ d_jkff
* u3 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ d_jkff
a1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ u2
a2 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ u3
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Control Statements

.ends 74HC107
1 change: 1 addition & 0 deletions library/SubcircuitLibrary/74HC107/74HC107_Previous_Values.xml
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<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /></KicadtoNgspice>
1 change: 1 addition & 0 deletions library/SubcircuitLibrary/74HC107/analysis
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.tran 0e-00 0e-00 0e-00
1 change: 1 addition & 0 deletions library/SubcircuitLibrary/74HC123/analysis
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.tran 0e-00 0e-00 0e-00
128 changes: 128 additions & 0 deletions library/SubcircuitLibrary/74HC123/multivibrator-cache.lib
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# PORT
#
DEF PORT U 0 40 Y Y 26 F N
F0 "U" 50 100 30 H V C CNN
F1 "PORT" 0 0 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
S -100 50 100 -50 0 1 0 N
X ~ 1 250 0 100 L 30 30 1 1 B
X ~ 2 250 0 100 L 30 30 2 1 B
X ~ 3 250 0 100 L 30 30 3 1 B
X ~ 4 250 0 100 L 30 30 4 1 B
X ~ 5 250 0 100 L 30 30 5 1 B
X ~ 6 250 0 100 L 30 30 6 1 B
X ~ 7 250 0 100 L 30 30 7 1 B
X ~ 8 250 0 100 L 30 30 8 1 B
X ~ 9 250 0 100 L 30 30 9 1 B
X ~ 10 250 0 100 L 30 30 10 1 B
X ~ 11 250 0 100 L 30 30 11 1 B
X ~ 12 250 0 100 L 30 30 12 1 B
X ~ 13 250 0 100 L 30 30 13 1 B
X ~ 14 250 0 100 L 30 30 14 1 B
X ~ 15 250 0 100 L 30 30 15 1 B
X ~ 16 250 0 100 L 30 30 16 1 B
X ~ 17 250 0 100 L 30 30 17 1 B
X ~ 18 250 0 100 L 30 30 18 1 B
X ~ 19 250 0 100 L 30 30 19 1 B
X ~ 20 250 0 100 L 30 30 20 1 B
X ~ 21 250 0 100 L 30 30 21 1 B
X ~ 22 250 0 100 L 30 30 22 1 B
X ~ 23 250 0 100 L 30 30 23 1 B
X ~ 24 250 0 100 L 30 30 24 1 B
X ~ 25 250 0 100 L 30 30 25 1 B
X ~ 26 250 0 100 L 30 30 26 1 B
ENDDRAW
ENDDEF
#
# adc_bridge_1
#
DEF adc_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "adc_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# d_tff
#
DEF d_tff U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "d_tff" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S 350 450 -350 -400 0 1 0 N
X T 1 -550 350 200 R 50 50 1 1 I
X Clk 2 -550 -300 200 R 50 50 1 1 I C
X Set 3 0 650 200 D 50 50 1 1 I
X Reset 4 0 -600 200 U 50 50 1 1 I
X Out 5 550 350 200 L 50 50 1 1 O
X Nout 6 550 -300 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# dac_bridge_1
#
DEF dac_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "dac_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# eSim_C
#
DEF eSim_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "eSim_C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS capacitor
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# eSim_R
#
DEF eSim_R R 0 0 N Y 1 F N
F0 "R" 50 130 50 H V C CNN
F1 "eSim_R" 50 -50 50 H V C CNN
F2 "" 50 -20 30 H V C CNN
F3 "" 50 50 30 V V C CNN
ALIAS resistor
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S 150 10 -50 90 0 1 10 N
X ~ 1 -100 50 50 R 60 60 1 1 P
X ~ 2 200 50 50 L 60 60 1 1 P
ENDDRAW
ENDDEF
#
#End Library
27 changes: 27 additions & 0 deletions library/SubcircuitLibrary/74HC123/multivibrator.cir
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* C:\FOSSEE\eSim\library\SubcircuitLibrary\multivibrator\multivibrator.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 11/24/25 10:00:12

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U7 Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad6_ Net-_U7-Pad4_ Net-_U11-Pad1_ ? d_tff
U4 Net-_U1-Pad4_ Net-_U4-Pad2_ adc_bridge_1
R4 Net-_C2-Pad1_ Net-_R4-Pad2_ 100k
C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 150n
U11 Net-_U11-Pad1_ Net-_C2-Pad1_ dac_bridge_1
U5 Net-_R2-Pad2_ Net-_U5-Pad2_ adc_bridge_1
U9 Net-_C2-Pad2_ Net-_U7-Pad4_ adc_bridge_1
R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 10k
U6 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U6-Pad4_ Net-_U10-Pad1_ ? d_tff
U2 Net-_U1-Pad3_ Net-_U2-Pad2_ adc_bridge_1
R3 Net-_C1-Pad1_ Net-_R3-Pad2_ 100k
C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 150n
U10 Net-_U10-Pad1_ Net-_C1-Pad1_ dac_bridge_1
U3 Net-_R1-Pad2_ Net-_U3-Pad2_ adc_bridge_1
U8 Net-_C1-Pad2_ Net-_U6-Pad4_ adc_bridge_1
R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 10k
U1 Net-_R2-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_C1-Pad2_ Net-_C2-Pad2_ Net-_R3-Pad2_ Net-_R4-Pad2_ PORT

.end
58 changes: 58 additions & 0 deletions library/SubcircuitLibrary/74HC123/multivibrator.cir.out
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* c:\fossee\esim\library\subcircuitlibrary\multivibrator\multivibrator.cir

* u7 net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? d_tff
* u4 net-_u1-pad4_ net-_u4-pad2_ adc_bridge_1
r4 net-_c2-pad1_ net-_r4-pad2_ 100k
c2 net-_c2-pad1_ net-_c2-pad2_ 150n
* u11 net-_u11-pad1_ net-_c2-pad1_ dac_bridge_1
* u5 net-_r2-pad2_ net-_u5-pad2_ adc_bridge_1
* u9 net-_c2-pad2_ net-_u7-pad4_ adc_bridge_1
r2 net-_r2-pad1_ net-_r2-pad2_ 10k
* u6 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? d_tff
* u2 net-_u1-pad3_ net-_u2-pad2_ adc_bridge_1
r3 net-_c1-pad1_ net-_r3-pad2_ 100k
c1 net-_c1-pad1_ net-_c1-pad2_ 150n
* u10 net-_u10-pad1_ net-_c1-pad1_ dac_bridge_1
* u3 net-_r1-pad2_ net-_u3-pad2_ adc_bridge_1
* u8 net-_c1-pad2_ net-_u6-pad4_ adc_bridge_1
r1 net-_r1-pad1_ net-_r1-pad2_ 10k
* u1 net-_r2-pad1_ net-_r1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_c2-pad2_ net-_r3-pad2_ net-_r4-pad2_ port
a1 net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? u7
a2 [net-_u1-pad4_ ] [net-_u4-pad2_ ] u4
a3 [net-_u11-pad1_ ] [net-_c2-pad1_ ] u11
a4 [net-_r2-pad2_ ] [net-_u5-pad2_ ] u5
a5 [net-_c2-pad2_ ] [net-_u7-pad4_ ] u9
a6 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? u6
a7 [net-_u1-pad3_ ] [net-_u2-pad2_ ] u2
a8 [net-_u10-pad1_ ] [net-_c1-pad1_ ] u10
a9 [net-_r1-pad2_ ] [net-_u3-pad2_ ] u3
a10 [net-_c1-pad2_ ] [net-_u6-pad4_ ] u8
* Schematic Name: d_tff, NgSpice Name: d_tff
.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u4 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u11 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u5 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u9 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_tff, NgSpice Name: d_tff
.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u10 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u8 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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