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reworks mstatus handling, #28

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Merged
eyck merged 8 commits into from
Dec 16, 2025
Merged

reworks mstatus handling, #28

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4b854a5
reworks mstatus handling,
EAlexJ Dec 14, 2025
cf5f081
fixes CLINT interrupt handling
eyck Dec 14, 2025
0f4bb16
adds initiator id for bus accesses
eyck Dec 15, 2025
605c236
changes mstatus default value for 64 bits to implement UXL and SXL reads
EAlexJ Dec 16, 2025
cedc491
moves mask generation for mstatus into common,
EAlexJ Dec 16, 2025
590cef2
Merge branch 'develop' into feature/better_mstatus
eyck Dec 16, 2025
84017d2
introduces bandaid fix for mstatus rst val
EAlexJ Dec 16, 2025
2ca7c80
caches conan dependencies in github action
EAlexJ Dec 16, 2025
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6 changes: 6 additions & 0 deletions .github/workflows/ci-compile.yml
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Expand Up @@ -31,6 +31,12 @@ jobs:

- name: Update submodules
run: git submodule update --init --recursive

- name: Cache Conan
uses: actions/cache@v4
with:
path: ~/.conan2
key: conan-${{ runner.os }}-unit-cpp${{ matrix.cpp_std }}-${{ hashFiles('conanfile.py') }}

- name: Install dependencies
run: |
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10 changes: 9 additions & 1 deletion src/iss/arch/mstatus.h
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Expand Up @@ -73,6 +73,8 @@ template <typename T> struct status<T, typename std::enable_if<std::is_same<T, u
static inline unsigned FS(T v) { return bit_sub<13, 2>(v); };
// machine previous privilege
static inline unsigned MPP(T v) { return bit_sub<11, 2>(v); };
// vector unit status Off/Initial/Clean/Dirty
static inline unsigned VS(T v) { return bit_sub<9, 2>(v); };
// supervisor previous privilege
static inline unsigned SPP(T v) { return bit_sub<8, 1>(v); };
// previous machine interrupt-enable
Expand Down Expand Up @@ -121,6 +123,8 @@ template <typename T> struct status<T, typename std::enable_if<std::is_same<T, u
static inline unsigned FS(T v) { return bit_sub<13, 2>(v); };
// machine previous privilege
static inline unsigned MPP(T v) { return bit_sub<11, 2>(v); };
// vector unit status Off/Initial/Clean/Dirty
static inline unsigned VS(T v) { return bit_sub<9, 2>(v); };
// supervisor previous privilege
static inline unsigned SPP(T v) { return bit_sub<8, 1>(v); };
// previous machine interrupt-enable
Expand Down Expand Up @@ -165,6 +169,8 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
BF_FIELD(FS, 13, 2);
// machine previous privilege
BF_FIELD(MPP, 11, 2);
// vector unit status Off/Initial/Clean/Dirty
BF_FIELD(VS, 9, 2);
// supervisor previous privilege
BF_FIELD(SPP, 8, 1);
// previous machine interrupt-enable
Expand Down Expand Up @@ -220,6 +226,8 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
BF_FIELD(FS, 13, 2);
// machine previous privilege
BF_FIELD(MPP, 11, 2);
// vector unit status Off/Initial/Clean/Dirty
BF_FIELD(VS, 9, 2);
// supervisor previous privilege
BF_FIELD(SPP, 8, 1);
// previous machine interrupt-enable
Expand All @@ -238,7 +246,7 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T

mstatus_t mstatus;

static const T mstatus_reset_val = 0x500001800;
static const T mstatus_reset_val = 0x1800;
};
} // namespace arch
} // namespace iss
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4 changes: 4 additions & 0 deletions src/iss/arch/riscv_hart_msu_vp.h
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Expand Up @@ -127,6 +127,10 @@ template <typename BASE, features_e FEAT>
riscv_hart_msu_vp<BASE, FEAT>::riscv_hart_msu_vp()
: mmu(base::get_priv_if())
, default_mem(base::get_priv_if()) {
if constexpr(sizeof(reg_t) == 8)
// set UXL and SXL to indicate 64 bits
// FIXME: this value is not preserved in resets
this->state.mstatus.backing.val |= 0x500000000;
// common regs
const std::array<unsigned, 16> rwaddrs{
{mepc, mtvec, mscratch, mcause, mtval, sepc, stvec, sscratch, scause, stval, sscratch, uepc, utvec, uscratch, ucause, utval}};
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