Spi dma irq

Cargo.toml

@@ -24,6 +24,7 @@ test-hmac = []
 test-hash = []
 spi_dma = []
 spi_dma_write = []
+spi_dma_irq = []
 spi_monitor = []
 
 [dependencies]
@@ -38,11 +39,12 @@ hex-literal = "0.4"
 heapless = "0.8.0"
 nb = "1.1.0"
 paste = "1.0"
+static_cell = "2"
 
 openprot-hal-blocking = { git="https://github.com/OpenPRoT/openprot" }
 zerocopy = { version = "0.8.25", features = ["derive"] }
-
-cortex-m = { version = "0.7.7" }
+critical-section = "1.2"
+cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
 cortex-m-rt = { version = "0.7.5", features = ["device"] }
 panic-halt = "1.0.0"
 

src/astdebug.rs

@@ -3,7 +3,7 @@
 use crate::uart_core::UartController;
 use embedded_io::Write;
 
-pub fn print_array_u32(uart: &mut UartController<'_>, data: &[u32]) {
+pub fn print_array_u32(uart: &mut UartController, data: &[u32]) {
     let bytes_per_line = 0x4;
     for (i, dw) in data.iter().enumerate() {
         if i.is_multiple_of(bytes_per_line) {
@@ -16,7 +16,7 @@ pub fn print_array_u32(uart: &mut UartController<'_>, data: &[u32]) {
     writeln!(uart, "\r").unwrap();
 }
 
-pub fn print_array_u8(uart: &mut UartController<'_>, data: &[u8]) {
+pub fn print_array_u8(uart: &mut UartController, data: &[u8]) {
     let bytes_per_line = 0x8;
     for (i, b) in data.iter().enumerate() {
         if i.is_multiple_of(bytes_per_line) {
@@ -29,7 +29,7 @@ pub fn print_array_u8(uart: &mut UartController<'_>, data: &[u8]) {
     writeln!(uart, "\r").unwrap();
 }
 
-pub fn print_reg_u8(uart: &mut UartController<'_>, reg_base: usize, size: usize) {
+pub fn print_reg_u8(uart: &mut UartController, reg_base: usize, size: usize) {
     let bytes_per_line = 0x8;
     let scu_bytes: &[u8] = unsafe { core::slice::from_raw_parts(reg_base as *const u8, size) };
 
@@ -44,7 +44,7 @@ pub fn print_reg_u8(uart: &mut UartController<'_>, reg_base: usize, size: usize)
     writeln!(uart, "\r").unwrap();
 }
 
-pub fn print_reg_u32(uart: &mut UartController<'_>, reg_base: usize, size: usize) {
+pub fn print_reg_u32(uart: &mut UartController, reg_base: usize, size: usize) {
     let words_per_line = 4; // 4 u32 values per line
     let reg_words: &[u32] =
         unsafe { core::slice::from_raw_parts(reg_base as *const u32, size / 4) };

src/common.rs

@@ -14,6 +14,15 @@ impl embedded_hal::delay::DelayNs for DummyDelay {
     }
 }
 
+pub fn fill_random(buf: &mut [u8], seed: &mut u32) {
+    for b in buf.iter_mut() {
+        *seed ^= *seed << 13;
+        *seed ^= *seed >> 17;
+        *seed ^= *seed << 5;
+        *b = (*seed & 0xFF) as u8;
+    }
+}
+
 #[repr(align(32))]
 pub struct DmaBuffer<const N: usize> {
     pub buf: [u8; N],

src/main.rs

@@ -18,14 +18,14 @@ use aspeed_ddk::{i2c_core, spi};
 use fugit::MillisDurationU32 as MilliSeconds;
 
 use aspeed_ddk::tests::functional::ecdsa_test::run_ecdsa_tests;
-use aspeed_ddk::tests::functional::gpio_test;
 use aspeed_ddk::tests::functional::hash_test::run_hash_tests;
 use aspeed_ddk::tests::functional::hmac_test::run_hmac_tests;
 use aspeed_ddk::tests::functional::i2c_core_test::run_i2c_core_tests;
 use aspeed_ddk::tests::functional::i2c_master_slave_test::run_master_slave_tests;
 use aspeed_ddk::tests::functional::i2c_test;
 use aspeed_ddk::tests::functional::rsa_test::run_rsa_tests;
 use aspeed_ddk::tests::functional::timer_test::run_timer_tests;
+use aspeed_ddk::tests::functional::{gpio_test, spim_test};
 use panic_halt as _;
 
 // Import owned API traits and types
@@ -327,13 +327,41 @@ fn main() -> ! {
     writeln!(uart_controller, "\r\nHello, world!!\r\n").unwrap();
 
     let delay = DummyDelay;
+
     let mut syscon = SysCon::new(delay.clone(), scu);
 
     // Enable HACE (Hash and Crypto Engine)
     let _ = syscon.enable_clock(ClockId::ClkYCLK as u8);
     let reset_id = ResetId::RstHACE;
     let _ = syscon.reset_deassert(&reset_id);
 
+    spi::spitest::show_spi_regiters(&mut uart_controller);
+    let test_spicontroller = false;
+    let test_irq = false;
+    if test_spicontroller {
+        spi::spidmairqtest::init_spidmairq_app_once();
+        if test_irq {
+            writeln!(uart_controller, "\r\nTEST SPI IRQ!!\r\n").unwrap();
+
+            spi::spidmairqtest::test_fmc_dma_irq(&mut uart_controller);
+            spi::spidmairqtest::test_spi_dma_irq(&mut uart_controller);
+        } else {
+            spi::spitest::test_fmc(&mut uart_controller);
+            spi::spitest::test_spi(&mut uart_controller);
+            //gpio_test::test_gpio_flash_power(&mut uart_controller);
+            // spi::spitest::test_spi2(&mut uart_controller);
+        }
+        let mut delay1 = DummyDelay;
+        delay1.delay_ns(10_000_000);
+    }
+    let spim_test = false;
+    if spim_test {
+        // use to release ast2600
+        spim_test::test_spim0(&mut uart_controller);
+        gpio_test::test_gpio_flash_power(&mut uart_controller);
+        gpio_test::test_gpio_bmc_reset(&mut uart_controller);
+    }
+
     let mut hace_controller = HaceController::new(hace);
 
     run_hash_tests(&mut uart_controller, &mut hace_controller);
@@ -352,6 +380,7 @@ fn main() -> ! {
     let mut rsa = AspeedRsa::new(&secure, delay);
     run_rsa_tests(&mut uart_controller, &mut rsa);
     gpio_test::test_gpioa(&mut uart_controller);
+
     i2c_test::test_i2c_master(&mut uart_controller);
     #[cfg(feature = "i2c_target")]
     i2c_test::test_i2c_slave(&mut uart_controller);
@@ -372,14 +401,6 @@ fn main() -> ! {
     test_wdt(&mut uart_controller);
     run_timer_tests(&mut uart_controller);
 
-    let test_spicontroller = false;
-    if test_spicontroller {
-        spi::spitest::test_fmc(&mut uart_controller);
-        spi::spitest::test_spi(&mut uart_controller);
-
-        gpio_test::test_gpio_flash_power(&mut uart_controller);
-        spi::spitest::test_spi2(&mut uart_controller);
-    }
     // Initialize the peripherals here if needed
     loop {
         cortex_m::asm::wfi();

src/spi/consts.rs

@@ -0,0 +1,56 @@
+// Licensed under the Apache-2.0 license
+
+// Constants (unchanged)
+pub(crate) const SPI_CONF_CE0_ENABLE_WRITE_SHIFT: u32 = 16;
+
+pub(crate) const SPI_CTRL_FREQ_MASK: u32 = 0x0F00_0F00;
+pub(crate) const SPI_CTRL_CEX_SPI_CMD_SHIFT: u32 = 16;
+pub(crate) const SPI_CTRL_CEX_SPI_CMD_MASK: u32 = 0xff;
+pub(crate) const SPI_CTRL_CEX_DUMMY_SHIFT: u32 = 6;
+pub(crate) const SPI_CTRL_CEX_4BYTE_MODE_SET: u32 = 0x11; // bit0: 4byte mode, bit4: 4byte mode cmd
+
+pub(crate) const SPI_DMA_DELAY_SHIFT: u32 = 8;
+pub(crate) const SPI_DMA_DELAY_MASK: u32 = 0xff;
+pub(crate) const SPI_DMA_CLK_FREQ_SHIFT: u32 = 16;
+pub(crate) const SPI_DMA_CLK_FREQ_MASK: u32 = 0xf;
+
+pub(crate) const SPI_DMA_GET_REQ_MAGIC: u32 = 0xaeed_0000;
+pub(crate) const SPI_DMA_DISCARD_REQ_MAGIC: u32 = 0xdeea_0000;
+pub(crate) const SPI_DMA_RAM_MAP_BASE: u32 = 0x8000_0000;
+pub(crate) const SPI_DMA_FLASH_MAP_BASE: u32 = 0x6000_0000;
+
+pub(crate) const SPI_CALIB_LEN: usize = 0x400;
+
+#[cfg(feature = "spi_dma")]
+pub(crate) const SPI_DMA_TRIGGER_LEN: u32 = 128;
+
+#[cfg(feature = "spi_dma")]
+pub(crate) const SPI_DMA_WRITE: u32 = 1 << 1;
+
+pub(crate) const SPI_DMA_REQUEST: u32 = 1 << 31;
+pub(crate) const SPI_DMA_GRANT: u32 = 1 << 30;
+pub(crate) const SPI_DMA_CALIB_MODE: u32 = 1 << 3;
+pub(crate) const SPI_DMA_CALC_CKSUM: u32 = 1 << 2;
+
+pub(crate) const SPI_DMA_ENABLE: u32 = 1 << 0;
+pub(crate) const SPI_DMA_STATUS: u32 = 1 << 11;
+
+pub(crate) const ASPEED_MAX_CS: usize = 5; // Must be usize for array indexing
+
+pub(crate) const ASPEED_SPI_NORMAL_READ: u32 = 0x1;
+pub(crate) const ASPEED_SPI_NORMAL_WRITE: u32 = 0x2;
+pub(crate) const ASPEED_SPI_USER: u32 = 0x3;
+pub(crate) const ASPEED_SPI_USER_INACTIVE: u32 = 0x4;
+
+pub(crate) const ASPEED_SPI_SZ_2M: u32 = 0x0020_0000;
+pub(crate) const ASPEED_SPI_SZ_256M: u32 = 0x1000_0000;
+
+pub(crate) const HPLL_FREQ: u32 = 1_000_000_000;
+
+pub(crate) const SPI_DMA_TIMEOUT: u32 = 0x10000;
+
+// SPIM clock output pin bits
+pub(crate) const PIN_SPIM0_CLK_OUT_BIT: u32 = 7;
+pub(crate) const PIN_SPIM1_CLK_OUT_BIT: u32 = 21;
+pub(crate) const PIN_SPIM2_CLK_OUT_BIT: u32 = 3;
+pub(crate) const PIN_SPIM3_CLK_OUT_BIT: u32 = 17;

src/spi/device.rs

@@ -1,40 +1,45 @@
 // Licensed under the Apache-2.0 license
 
+use crate::spimonitor::SpiMonitorNum;
+
 use super::SpiBusWithCs;
 use super::SpiError;
-use crate::spimonitor::{SpiMonitor, SpipfInstance};
 use embedded_hal::spi::{ErrorType, Operation, SpiDevice};
 
 #[derive(Debug)]
-pub struct ChipSelectDevice<'a, B, SPIPF>
+pub struct ChipSelectDevice<'a, B>
 where
     B: SpiBusWithCs,
-    SPIPF: SpipfInstance,
 {
     pub bus: &'a mut B,
     pub cs: usize,
-    pub spi_monitor: Option<&'a mut SpiMonitor<SPIPF>>,
+    pub spim: Option<SpiMonitorNum>,
 }
 
-impl<B, SPIPF> ErrorType for ChipSelectDevice<'_, B, SPIPF>
+impl<B> ErrorType for ChipSelectDevice<'_, B>
 where
     B: SpiBusWithCs,
-    SPIPF: SpipfInstance,
 {
     type Error = B::Error;
 }
 
-impl<B, SPIPF> SpiDevice for ChipSelectDevice<'_, B, SPIPF>
+impl From<SpiMonitorNum> for u32 {
+    #[inline]
+    fn from(v: SpiMonitorNum) -> u32 {
+        v as u32
+    }
+}
+
+impl<B> SpiDevice for ChipSelectDevice<'_, B>
 where
     B: SpiBusWithCs,
-    SPIPF: SpipfInstance,
 {
     fn transaction(&mut self, operations: &mut [Operation<'_, u8>]) -> Result<(), SpiError> {
         self.bus.select_cs(self.cs)?;
-        if let Some(spim) = self.spi_monitor.as_mut() {
+        if let Some(spim) = self.spim {
             if self.bus.get_master_id() != 0 {
-                spim.spim_scu_ctrl_set(0x8, 0x8);
-                spim.spim_scu_ctrl_set(0x7, 1 + SPIPF::FILTER_ID as u32);
+                super::spim_scu_ctrl_set(0x8, 0x8);
+                super::spim_scu_ctrl_set(0x7, 1 + u32::from(spim));
             }
             super::spim_proprietary_pre_config();
         }
@@ -45,17 +50,15 @@ where
                 Operation::Write(buf) => self.bus.write(buf)?,
                 Operation::Transfer(read, write) => self.bus.transfer(read, write)?,
                 Operation::TransferInPlace(buf) => self.bus.transfer_in_place(buf)?,
-                Operation::DelayNs(_) => todo!(),
+                Operation::DelayNs(_) => {} // Ignore delay, as the SPI controller will handle timing
             }
         }
-
-        super::spim_proprietary_post_config();
-        if let Some(spim) = self.spi_monitor.as_mut() {
+        if let Some(_spim) = self.spim {
+            super::spim_proprietary_post_config();
             if self.bus.get_master_id() != 0 {
-                spim.spim_scu_ctrl_clear(0xf);
+                super::spim_scu_ctrl_clear(0xf);
             }
         }
-        self.bus.deselect_cs(self.cs)?;
         Ok(())
     }
 

src/spi/error.rs

@@ -0,0 +1,33 @@
+// Licensed under the Apache-2.0 license
+
+use embedded_hal::spi;
+
+#[derive(Debug)]
+pub enum SpiError {
+    BusError,
+    DmaTimeout,
+    CsSelectFailed(usize),
+    LengthMismatch,
+    CapacityOutOfRange,
+    UnsupportedDevice(u8),
+    AddressNotAligned(u32),
+    InvalidCommand(u8),
+    Other(&'static str),
+}
+
+/// Required by embedded-hal 1.0
+impl spi::Error for SpiError {
+    fn kind(&self) -> spi::ErrorKind {
+        match self {
+            SpiError::BusError
+            | SpiError::DmaTimeout
+            | SpiError::CsSelectFailed(_)
+            | SpiError::LengthMismatch
+            | SpiError::CapacityOutOfRange
+            | SpiError::UnsupportedDevice(_)
+            | SpiError::InvalidCommand(_)
+            | SpiError::AddressNotAligned(_)
+            | SpiError::Other(_) => spi::ErrorKind::Other,
+        }
+    }
+}