GitHub - PrajwalShenoy/Final-Year-Project

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 143 Commits
16_Bit_processor		16_Bit_processor
Assembler.py-master-20200209T075256Z-001.zip		Assembler.py-master-20200209T075256Z-001.zip
README		README
VLSI_Manual_new.pdf		VLSI_Manual_new.pdf
Verilog HDL - Samir Palnitkar.pdf		Verilog HDL - Samir Palnitkar.pdf
a_reg.v		a_reg.v
alu.v		alu.v
alu_tb.v		alu_tb.v
and16.v		and16.v
and16_tb.v		and16_tb.v
andg.v		andg.v
andg_tb.v		andg_tb.v
cpu.v		cpu.v
cpu_tb.v		cpu_tb.v
d_reg.v		d_reg.v
decode.v		decode.v
decode_tb.v		decode_tb.v
decoder.v		decoder.v
dff.v		dff.v
dff16.v		dff16.v
dff16_tb.v		dff16_tb.v
dff_tb.v		dff_tb.v
dmux.v		dmux.v
dmux16.v		dmux16.v
dmux16_4.v		dmux16_4.v
dmux16_4_tb.v		dmux16_4_tb.v
dmux16_8.v		dmux16_8.v
dmux16_8_tb.v		dmux16_8_tb.v
dmux16_tb.v		dmux16_tb.v
dmux_tb.v		dmux_tb.v
full_adder.v		full_adder.v
full_adder16.v		full_adder16.v
full_adder16_tb.v		full_adder16_tb.v
full_adder_tb.v		full_adder_tb.v
half_adder.v		half_adder.v
half_adder_tb.v		half_adder_tb.v
incrementer.v		incrementer.v
incrementer_tb.v		incrementer_tb.v
is_equal.v		is_equal.v
is_equal_tb.v		is_equal_tb.v
load.v		load.v
load_tb.v		load_tb.v
make.sh		make.sh
mux.v		mux.v
mux16.v		mux16.v
mux16_4.v		mux16_4.v
mux16_4_tb.v		mux16_4_tb.v
mux16_8.v		mux16_8.v
mux16_8_tb.v		mux16_8_tb.v
mux16_tb.v		mux16_tb.v
mux_8.v		mux_8.v
mux_8_tb.v		mux_8_tb.v
mux_tb.v		mux_tb.v
not16.v		not16.v
not16_tb.v		not16_tb.v
notg.v		notg.v
notg_tb.v		notg_tb.v
or16.v		or16.v
or16_tb.v		or16_tb.v
org.v		org.v
org_8.v		org_8.v
org_8_tb.v		org_8_tb.v
org_tb.v		org_tb.v
program_counter.v		program_counter.v
program_counter_tb.v		program_counter_tb.v
register.v		register.v
register16.v		register16.v
register16_tb.v		register16_tb.v
register_tb.v		register_tb.v
xorg.v		xorg.v
xorg_tb.v		xorg_tb.v

Repository files navigation

Paarthvi
Done
AND gate 
OR gate 
16 bit AND gate
8 bit OR gate
16 bit OR gate
ALU
is_equal_to
Mux 8:1
load computation
NotDone

Aldrich
Done
DMUX 1:2
script to create log files
NotDone
Assembler

Sanath 
Done
HALFADDER
FULLADDER
XOR gate
16 bit FULLADDER
16 bit INCREMENTER
Decoder and test bench
NotDone
The drawing of the entire Computer

Prajwal
Done
NOT (MOS level)
16 bit NOT gate
MUX 2:1
MUX 16bit 2:1
MUX 16bit 8:1
MUX 16bit 4:1
DMUX 16bit 1:2
DMUX 16bit 1:4
DMUX 16bit 1:8
ALU
is_equal_to
Register 1bit
Register 16bit
Program Counter
A register
D register

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Things that need to be done.
RAM and ROM are needed for the simulation and need not be built using flipflops