Remove strict stride multiple enforcement for expanded tensor support#2226
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justinrosner merged 6 commits intodevelopfrom Feb 4, 2026
Merged
Remove strict stride multiple enforcement for expanded tensor support#2226justinrosner merged 6 commits intodevelopfrom
justinrosner merged 6 commits intodevelopfrom
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Pull request overview
This PR removes an overly restrictive stride validation check that was preventing MIGraphX from compiling valid concat kernels. The check required memory layout dimensions to be integer multiples of logical tensor dimensions, which failed for cases where a kernel writes to a non-contiguous slice of a concatenated output buffer.
Changes:
- Removed the modulo check in
AsUnderlyingShapeConverterthat enforced integer-multiple relationship between memory layout and logical dimensions - Added a positive test case demonstrating 4x5x24 logical tensor with 4x12x24 memory layout (non-multiple expansion)
- Removed the negative test case that was validating the now-removed error condition
Reviewed changes
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| File | Description |
|---|---|
| mlir/lib/Conversion/MIGraphXToTosa/MIGraphXToTosa.cpp | Removes 4-line modulo validation check that was rejecting valid non-contiguous output buffer strides |
| mlir/test/Conversion/MIGraphXToTosa/migraphx-to-tosa-non-contiguous-strides.mlir | Adds positive test for non-multiple expansion (4x5x24→4x12x24) and removes obsolete negative test case |
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I still get a similar error: Which might come from here: |
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Removed that check as well. I'm assuming this is from running the second kernel? |
dhernandez0
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dhernandez0
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Feb 4, 2026
dhernandez0
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Motivation
This PR removes a strict check in MIGraphXToTosa that was preventing MIGraphX from compiling certain concat kernels. This implements: https://amd-hub.atlassian.net/browse/AIROCMLIR-472
Technical Details
The
AsUnderlyingShapeConverterwas incorrectly rejecting valid non-contiguous output buffer strides. Specifically, it required that memory layout dimensions be integer multiples of the logical tensor dimensions. This failed for cases like<4x5x24xf16, 288x24x1>where the logical shape is 4x5x24 but the memory layout is 4x12x24. This pattern could occur when MIGraphX concatenates tensors (e.g., a 4x5x24 and 4x7x24 into a 4x12x24 buffer), where each kernel writes to a different slice of the final buffer.Test Plan
Test Result
Submission Checklist