Fixes for Cocotb v2

.github/workflows/regression-tests.yml

@@ -46,7 +46,7 @@ jobs:
             python-version: '3.10'
 
           - sim: verilator
-            sim-version: v5.020
+            sim-version: v5.044
             python-version: '3.10'
             pytest-marker: "-m verilator"
 
@@ -67,7 +67,7 @@ jobs:
     - name: Install Python dependencies
       shell: bash -l {0}
       run: |
-        pip install pyvisa pyvisa-sim pytest coveralls pytest-cov cocotb>=1.8.1 cocotb-bus
+        pip install pyvisa pyvisa-sim pytest coveralls pytest-cov cocotb>=2 cocotb-bus
 
     - name: Install Verilator
       if: matrix.sim == 'verilator'

basil/firmware/modules/spi/spi_core.v

@@ -11,13 +11,16 @@ module spi_core #(
     parameter ABUSWIDTH = 16,
     parameter MEM_BYTES = 16
 ) (
-    input wire                      BUS_CLK,
-    input wire                      BUS_RST,
-    input wire     [ABUSWIDTH-1:0]  BUS_ADD,
-    input wire     [7:0]            BUS_DATA_IN,
-    input wire                      BUS_RD,
-    input wire                      BUS_WR,
-    output reg [7:0]                BUS_DATA_OUT,
+    input wire                 BUS_CLK,
+    input wire                 BUS_RST,
+    input wire [ABUSWIDTH-1:0] BUS_ADD,
+    /* verilator lint_off UNOPTFLAT */
+    // Clocked and safe in synthesis, else circular logic data_in -> memory -> data_out
+    input wire [7:0]           BUS_DATA_IN,
+    /* verilator lint_on UNOPTFLAT */
+    input wire                 BUS_RD,
+    input wire                 BUS_WR,
+    output reg [7:0]           BUS_DATA_OUT,
 
     input wire SPI_CLK,
 

basil/firmware/modules/utils/RAMB16_S1_S9_sim.v

@@ -47,7 +47,10 @@ localparam minWIDTH  = `min(WIDTHA, WIDTHB);
 localparam RATIO     = maxWIDTH / minWIDTH;
 localparam log2RATIO = `CLOG2(RATIO);
 
-reg     [minWIDTH-1:0]  RAM [0:maxSIZE-1];
+/* verilator lint_off MULTIDRIVEN */
+// In synthesis, uses IP block; in this model, memory is multi-driven
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+/* verilator lint_on MULTIDRIVEN */
 
 always @(posedge CLKA)
   if (WEA)

basil/utils/sim/BasilBusDriver.py

@@ -10,7 +10,7 @@
 # pylint: disable=pointless-statement, expression-not-assigned
 
 
-from cocotb.binary import BinaryValue
+from cocotb.types import LogicArray
 from cocotb.triggers import RisingEdge, Timer
 from cocotb_bus.drivers import BusDriver
 
@@ -24,13 +24,11 @@ class BasilBusDriver(BusDriver):
     def __init__(self, entity):
         BusDriver.__init__(self, entity, "", entity.BUS_CLK)
 
-        # Create an appropriately sized high-impedence value
-        self._high_impedence = BinaryValue(n_bits=len(self.bus.BUS_DATA))
-        self._high_impedence.binstr = "Z" * len(self.bus.BUS_DATA)
+        # Create an appropriately sized high-impedance value
+        self._high_impedance = LogicArray("Z" * len(self.bus.BUS_DATA))
 
-        # Create an appropriately sized high-impedence value
-        self._x = BinaryValue(n_bits=len(self.bus.BUS_ADD))
-        self._x.binstr = "x" * len(self.bus.BUS_ADD)
+        # Create an appropriately sized high-impedance value
+        self._x = LogicArray("x" * len(self.bus.BUS_ADD))
 
         self._has_byte_acces = False
 
@@ -40,7 +38,7 @@ async def init(self):
         self.bus.BUS_RD.value = 0
         self.bus.BUS_WR.value = 0
         self.bus.BUS_ADD.value = self._x
-        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_DATA.value = self._high_impedance
 
         for _ in range(8):
             await RisingEdge(self.clock)
@@ -61,7 +59,7 @@ async def init(self):
     async def read(self, address, size):
         result = []
 
-        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_DATA.value = self._high_impedance
         self.bus.BUS_ADD.value = self._x
         self.bus.BUS_RD.value = 0
 
@@ -79,33 +77,32 @@ async def read(self, address, size):
             await RisingEdge(self.clock)
 
             if byte != 0:
-                if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
-                    result.append(self.bus.BUS_DATA.value.integer & 0x000000FF)
-                    result.append((self.bus.BUS_DATA.value.integer & 0x0000FF00) >> 8)
-                    result.append((self.bus.BUS_DATA.value.integer & 0x00FF0000) >> 16)
-                    result.append((self.bus.BUS_DATA.value.integer & 0xFF000000) >> 24)
+                if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
+                    result.append(self.bus.BUS_DATA.value.to_unsigned() & 0x000000FF)
+                    result.append((self.bus.BUS_DATA.value.to_unsigned() & 0x0000FF00) >> 8)
+                    result.append((self.bus.BUS_DATA.value.to_unsigned() & 0x00FF0000) >> 16)
+                    result.append((self.bus.BUS_DATA.value.to_unsigned() & 0xFF000000) >> 24)
                 else:
-                    #    result.append(self.bus.BUS_DATA.value[24:31].integer & 0xff)
                     if len(self.bus.BUS_DATA.value) == 8:
-                        result.append(self.bus.BUS_DATA.value.integer & 0xFF)
+                        result.append(self.bus.BUS_DATA.value.to_unsigned() & 0xFF)
                     else:
-                        result.append(self.bus.BUS_DATA.value[24:31].integer & 0xFF)
+                        result.append(self.bus.BUS_DATA.value[7:0].to_unsigned() & 0xFF)
 
-            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
+            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
                 byte += 4
             else:
                 byte += 1
 
         self.bus.BUS_ADD.value = self._x
-        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_DATA.value = self._high_impedance
         await RisingEdge(self.clock)
 
         return result
 
     async def write(self, address, data):
 
         self.bus.BUS_ADD.value = self._x
-        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_DATA.value = self._high_impedance
         self.bus.BUS_WR.value = 0
 
         await RisingEdge(self.clock)
@@ -121,10 +118,10 @@ async def write(self, address, data):
 
             await RisingEdge(self.clock)
 
-        if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
+        if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
             raise NotImplementedError("BUS_BYTE_ACCESS for write to be implemented.")
 
-        self.bus.BUS_DATA.value = self._high_impedence
+        self.bus.BUS_DATA.value = self._high_impedance
         self.bus.BUS_ADD.value = self._x
         self.bus.BUS_WR.value = 0
 

basil/utils/sim/BasilSbusDriver.py

@@ -8,7 +8,7 @@
 # pylint: disable=pointless-statement, expression-not-assigned
 
 
-from cocotb.binary import BinaryValue
+from cocotb.types import LogicArray
 from cocotb.triggers import RisingEdge, ReadOnly
 from cocotb_bus.drivers import BusDriver
 
@@ -23,12 +23,10 @@ def __init__(self, entity):
         BusDriver.__init__(self, entity, "", entity.BUS_CLK, case_insensitive=False)
 
         # Create an appropriately sized high-impedance value
-        self._high_impedance = BinaryValue(n_bits=len(self.bus.BUS_DATA_IN))
-        self._high_impedance.binstr = "Z" * len(self.bus.BUS_DATA_IN)
+        self._high_impedance = LogicArray("Z" * len(self.bus.BUS_DATA_IN))
 
         # Create an appropriately sized high-impedance value
-        self._x = BinaryValue(n_bits=len(self.bus.BUS_ADD))
-        self._x.binstr = "x" * len(self.bus.BUS_ADD)
+        self._x = LogicArray("x" * len(self.bus.BUS_ADD))
 
         self._has_byte_acces = False
 
@@ -73,7 +71,7 @@ async def read(self, address, size):
 
             await RisingEdge(self.clock)
 
-            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
+            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
                 byte += 4
             else:
                 byte += 1
@@ -86,15 +84,15 @@ async def read(self, address, size):
 
             value = self.bus.BUS_DATA_OUT.value
 
-            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
-                result.append(value.integer & 0x000000FF)
-                result.append((value.integer & 0x0000FF00) >> 8)
-                result.append((value.integer & 0x00FF0000) >> 16)
-                result.append((value.integer & 0xFF000000) >> 24)
+            if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
+                result.append(value.to_unsigned() & 0x000000FF)
+                result.append((value.to_unsigned() & 0x0000FF00) >> 8)
+                result.append((value.to_unsigned() & 0x00FF0000) >> 16)
+                result.append((value.to_unsigned() & 0xFF000000) >> 24)
             elif len(value) == 8:
-                result.append(value.integer & 0xFF)
+                result.append(value.to_unsigned() & 0xFF)
             else:
-                result.append(value[24:31].integer & 0xFF)
+                result.append(value[7:0].to_unsigned() & 0xFF)
 
         await RisingEdge(self.clock)
 
@@ -114,7 +112,7 @@ async def write(self, address, data):
 
             await RisingEdge(self.clock)
 
-        if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0:
+        if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value == 0:
             raise NotImplementedError("BUS_BYTE_ACCESS for write to be implemented.")
 
         self.bus.BUS_ADD.value = self._x

basil/utils/sim/SiLibUsbBusDriver.py

@@ -12,7 +12,7 @@
 """
 Abastract away interactions with the control bus
 """
-from cocotb.binary import BinaryValue
+from cocotb.types import LogicArray
 from cocotb.triggers import RisingEdge, ReadOnly, Timer
 from cocotb_bus.drivers import BusDriver
 
@@ -34,12 +34,10 @@ def __init__(self, entity):
         BusDriver.__init__(self, entity, "", entity.FCLK_IN)
 
         # Create an appropriately sized high-impedance value
-        self._high_impedance = BinaryValue(n_bits=len(self.bus.BUS_DATA))
-        self._high_impedance.binstr = "Z" * len(self.bus.BUS_DATA)
+        self._high_impedance = LogicArray("Z" * len(self.bus.BUS_DATA))
 
         # Create an appropriately sized high-impedance value
-        self._x = BinaryValue(n_bits=16)
-        self._x.binstr = "x" * 16
+        self._x = LogicArray("x" * 16)
 
     async def init(self):
         # Defaults
@@ -104,7 +102,7 @@ async def read_external(self, address):
         await RisingEdge(self.clock)
         self.bus.RD_B.value = 0
         await ReadOnly()
-        result = self.bus.BUS_DATA.value.integer
+        result = self.bus.BUS_DATA.value.to_unsigned()
         await RisingEdge(self.clock)
         self.bus.RD_B.value = 1
 
@@ -161,7 +159,7 @@ async def fast_block_read(self):
         self.bus.FREAD.value = 1
         self.bus.FSTROBE.value = 1
         await ReadOnly()
-        result = self.bus.FD.value.integer
+        result = self.bus.FD.value.to_unsigned()
         await RisingEdge(self.clock)
         self.bus.FREAD.value = 0
         self.bus.FSTROBE.value = 0

basil/utils/sim/Test.py

@@ -73,11 +73,11 @@ async def test(dut, debug=False):
 
     # Kick off a clock generator
     if bus_clock:
-        cocotb.fork(Clock(bus.clock, bus_clk_freq).start())
+        cocotb.start_soon(Clock(bus.clock, bus_clk_freq).start())
 
     # start sim_modules
     for mod in sim_modules:
-        cocotb.fork(mod.run())
+        cocotb.start_soon(mod.run())
 
     await bus.init()
 

examples/MIO/src/example.v

@@ -26,8 +26,6 @@ module example (
     output wire LED4,
     output wire LED5,
 
-    inout wire FPGA_BUTTON,
-
     inout wire SDA,
     inout wire SCL
 );
@@ -58,7 +56,7 @@ localparam GPIO_BASEADDR = 16'h0000;
 localparam GPIO_HIGHADDR = 16'h000f;
 
 // USER MODULES //
-wire [1:0] GPIO_NOT_USED;
+wire [2:0] GPIO_NOT_USED;
 gpio #(
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
@@ -72,10 +70,10 @@ gpio #(
     .BUS_DATA(BUS_DATA),
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
-    .IO({FPGA_BUTTON, GPIO_NOT_USED, LED5, LED4, LED3, LED2, LED1})
+    .IO({GPIO_NOT_USED, LED5, LED4, LED3, LED2, LED1})
 );
 
-assign GPIO_NOT_USED = {LED2, LED1};
+assign GPIO_NOT_USED = {1'b0, LED2, LED1};
 
 //For simulation
 initial begin
@@ -87,8 +85,4 @@ assign SDA = 1'bz;
 assign SCL = 1'bz;
 assign DEBUG_D = 16'ha5a5;
 
-`ifdef COCOTB_SIM
-    assign FPGA_BUTTON = 0;
-`endif
-
 endmodule

examples/MIO/src/mio.ucf

@@ -183,7 +183,7 @@ NET "LED1" LOC = P13;
 
 # ------ Button & Spare & more -------------------------------------
 
-NET "FPGA_BUTTON"       LOC=P4		|	IOSTANDARD = LVCMOS33;
+#NET "FPGA_BUTTON"       LOC=P4		|	IOSTANDARD = LVCMOS33;
 #NET "FPGA_SPARE_1"      LOC=C16		|	IOSTANDARD = LVCMOS33;
 #NET "FPGA_SPARE_2"      LOC=K6		|	IOSTANDARD = LVCMOS33;
 

tests/test_SimGpio.v

@@ -25,7 +25,7 @@
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
-    input wire  [15:0]  BUS_ADD,
+    input wire  [31:0]  BUS_ADD,
 `ifndef SPLIT_BUS
     inout wire  [7:0]   BUS_DATA,
 `else
@@ -42,6 +42,8 @@ localparam GPIO_HIGHADDR = 16'h000f;
 localparam GPIO2_BASEADDR = 16'h0010;
 localparam GPIO2_HIGHADDR = 16'h001f;
 
+localparam ABUSWIDTH = 32;
+
 // Connect tb internal bus to external split bus
 `ifdef BASIL_TOPSBUS
     wire [7:0] BUS_DATA;
@@ -67,6 +69,7 @@ gpio_sbus #(
 `endif
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
+    .ABUSWIDTH(ABUSWIDTH),
     .IO_WIDTH(24),
     .IO_DIRECTION(24'h0000ff),
     .IO_TRI(24'hff0000)

tests/test_SimJtagGpio.v

@@ -14,7 +14,7 @@
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
-    input wire  [15:0]  BUS_ADD,
+    input wire  [31:0]  BUS_ADD,
     inout wire  [7:0]   BUS_DATA,
     input wire          BUS_RD,
     input wire          BUS_WR