Documentation, formatting, and linting for several modules: seq_gen, fast_spi_rx, gpio, spi, pulse_gen#272
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kcaisley wants to merge 39 commits into
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Documentation, formatting, and linting for several modules: seq_gen, fast_spi_rx, gpio, spi, pulse_gen#272kcaisley wants to merge 39 commits into
seq_gen, fast_spi_rx, gpio, spi, pulse_gen#272kcaisley wants to merge 39 commits into
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Add `ifndef/`define/`endif guards around `bus_to_ip.v` and `cdc_pulse_sync.v` includes in all basil module files that use them. These two utilities are shared across multiple module subtrees (fast_spi_rx, pulse_gen, gpio, spi, seq_gen), so the include guards prevent MODDUP warnings when the module tree is pulled in from a common parent (e.g. daq_core.v). Only a subset of missing imports are addressed here as a starting point for testing the import pattern. All other transitive dependencies across the basil module tree should be wired up following the same pattern.
Add a standalone Python script for verifying and documenting FPGA/ASIC register address maps. The tool: - Parses Verilog module port/parameter definitions for bus interfaces - Parses YAML register-map descriptions (basil-style) - Generates Markdown tables and ASCII-address-space diagrams - Detects overlapping address ranges and out-of-range assignments Useful as a CI gate to catch address-map bugs before synthesis.
- Rename _sim.v files to match module names (BUFG, IBUFDS, etc.) - Add new simulation models for missing primitives (IBUF, OBUF, IOBUF, ODDR, PLLE2_BASE) - Add behavioral implementations for buffer primitives - Keep copyright headers and formatting consistent with existing style
…thods - Add DATA_SIZE parameter to fast_spi_rx_core.v and fast_spi_rx.v - Frame counter width, SPI data width, and bit counter threshold all depend on DATA_SIZE - Add get_data_size() and parse_word() to Python driver for variable-width FIFO word parsing - Add FIFO_DATA register (addr 4, 32-bit) to register map - Fix minor whitespace/comment formatting in sitcp_fifo.py and seq_gen_core.v
Document set_en/get_en, get_lost_count, set_size/get_size, parse_word, and improve existing reset docstring with reset behavior details.
Explain output enable mask, IO_TRI requirement, and StdRegister usage.
…repeat, get_repeat, is_done Clarify delay is in clock cycles, explain @Property decorator and relationship between is_ready and is_done.
Document all registers, start/reset behavior, repeat mode (0=forever), external start, nested loops, and property/alias relationships.
…, get_data, reset Document READY register, memory size, and clarify reset aborts transfers.
Add unit test placeholder, usage notes (data format, FIFO flush, reset), and standardize section order to match seq_gen/spi/gpio/pulse_gen.
Add operational notes on tracks, start/repeat modes, output hold, and START/READY address aliasing. Fix 'friving' typo.
Rename BIT_OUT to SIZE, CONF_EN to EN. Add notes on external start, repeat mode, and START/DONE address aliasing.
Document StdRegister field-level access and pin direction behavior.
… address Add notes on start/repeat modes and START/READY address aliasing.
In RST, single backticks render as italics, not monospace. Switch all register/pin names to double backticks (START, DONE, READY, EN, etc.) so they render as code font.
Combine RESET/VERSION (addr 0) and START/DONE/READY (addr 1) into single rows with slashed names and wo/ro access notation, making the address aliasing clear in the register tables themselves.
- Add DATA_SIZE register (addr 4, ro) to the register decode in fast_spi_rx_core.v so the hardware parameter can be read back - Remove set_size from the Python driver; get_size now reads HW - Remove DATA_SIZE from YAML config (no longer needed) - Fix typo 'syncrhonized' -> 'synchronized' in fast_spi_rx_core.v - Fix docstring style: opening """ on its own line for multi-line - Delete bus_check.py utility (to be rewritten later) - Add Kian, Christian, and Rasmus to authors list in pyproject.toml
- Add module-level docstring - Add missing docstrings for __init__, init, get_nested_start, get_nested_stop, get_nested_repeat, get_mem_size - Fix D205: blank line between summary line and description - Break long single-line docstrings into multi-line with summary and description sections
- Add missing module-level, __init__, and method docstrings - Fix D205: blank line between summary line and description - Fix D200/D212: collapse multi-line single-liners - Fix D400/D401/D415: imperative mood, periods, single-line convention - Fix D413: blank line after Args/Returns sections
Add DATA_SIZE read-only register at addr 4 requires version bump from 0 to 1. Update _require_version in Python driver to match.
- Add DATA_SIZE register (addr 4, ro) to the register decode in fast_spi_rx_core.v so the hardware parameter can be read back - Remove set_size from the Python driver; get_size now reads HW - Remove DATA_SIZE from YAML config (no longer needed) - Fix typo 'syncrhonized' -> 'synchronized' in fast_spi_rx_core.v - Fix docstring style: opening """ on its own line for multi-line - Delete bus_check.py utility (to be rewritten later) - Add Kian, Christian, and Rasmus to authors list in pyproject.toml
cbespin
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May 21, 2026
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As we discussed, this looks good.
Only thing to keep it somewhere for people finding this PR when looking for breaking changes: using the IBUF, IDDR, etc replacements in simulation will require adjusting the include in the testbenches
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Could you take a look at the failing tests? I assume this originates from the include safeguards that are interfering with the includes in the tests / examples. |
Require the fast_spi_rx hardware layer to match the existing firmware version 1.
Verilator treats warnings as fatal where Icarus accepts the code. Size the fast SPI concatenation explicitly and elaborate only the writable RAM ports used by each SPI memory instance.
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I'm opening a pull here, to merge in some of the incremental changes I've been making. The changes are broadly:
fast_spi_rxmodules, so that it supports variable output data sizefast_spi_rxmoduleblk_mem_gen_8_to_1_2k, instead of hardcodedRAMB16_S1_S9