Fix the direction in Metadata for ddr bandwidth metric sets#56
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garimadhaked wants to merge 2 commits intoXilinx:masterfrom
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Fix the direction in Metadata for ddr bandwidth metric sets#56garimadhaked wants to merge 2 commits intoXilinx:masterfrom
garimadhaked wants to merge 2 commits intoXilinx:masterfrom
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… AIE dtrace Add new metric sets for interface tiles that configure both PORT_RUNNING and PORT_STALL events per channel, enabling peak bandwidth calculation. For peak_read_bandwidth (S2MM channels - read from DDR): - Counter 0: PORT_RUNNING_0 (Ch0 bytes transferred) - Counter 1: PORT_STALLED_0 (Ch0 stall cycles) - Counter 2: PORT_RUNNING_1 (Ch1 bytes transferred) - Counter 3: PORT_STALLED_1 (Ch1 stall cycles) For peak_write_bandwidth (MM2S channels - write to DDR): - Counter 0: PORT_RUNNING_0 (Ch0 bytes transferred) - Counter 1: PORT_STALLED_0 (Ch0 stall cycles) - Counter 2: PORT_RUNNING_1 (Ch1 bytes transferred) - Counter 3: PORT_STALLED_1 (Ch1 stall cycles) This enables post-processing to calculate: - Peak BW = Total Bytes / Running Cycles (excludes stall time) - Efficiency = Running Cycles / (Running Cycles + Stall Cycles) Signed-off-by: Garima Dhaked <garima.dhaked@amd.com> Made-with: Cursor
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