Skip to content

20.4.0.00013 #9

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
mattnite merged 2 commits into from
Dec 22, 2025
Merged

20.4.0.00013 #9

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
87b5f2a
20.4.0.00013
mattnite Dec 22, 2025
8f08cb5
commit targetdb, version 20.4.0.00013
actions-user Dec 22, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
6 changes: 3 additions & 3 deletions .github/workflows/build.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,9 @@ env:
REGISTRY: ghcr.io
IMAGE_NAME: ccstudio
MAJOR_VER: 20
MINOR_VER: 3
PATCH_VER: 1
BUILD_VER: "00005"
MINOR_VER: 4
PATCH_VER: 0
BUILD_VER: "00013"
COMPONENTS: PF_SITARA_MCU,PF_ARM_MPU,PF_C28,PF_C6000SC,PF_HERCULES,PF_MMWAVE,PF_MSP430,PF_MSPM0,PF_MSPM33,PF_OMAPL,PF_PGA,PF_MSP432,PF_AUTO,PF_TM4C,PF_DIGITAL_POWER,PF_WCONN

jobs:
Expand Down
109 changes: 109 additions & 0 deletions targetdb/Modules/C2000/f28p551x_access_protection_regs.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,109 @@
<module id="ACCESS_PROTECTION_REGS" HW_revision="" description="ACCESS PROTECTION Registers">
<register id="NMAVFLG" width="32" page="1" offset="0x0" internal="0" description="Non-Controller Access Violation Flag Register">
<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag" begin="0" end="0" width="1" rwaccess="R"/>
<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag" begin="1" end="1" width="1" rwaccess="R"/>
<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag" begin="2" end="2" width="1" rwaccess="R"/>
<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag" begin="3" end="3" width="1" rwaccess="R"/>
<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag" begin="4" end="4" width="1" rwaccess="R"/>
<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag" begin="5" end="5" width="1" rwaccess="R"/>
<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag" begin="6" end="6" width="1" rwaccess="R"/>
<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag" begin="10" end="10" width="1" rwaccess="R"/>
<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag" begin="11" end="11" width="1" rwaccess="R"/>
<bitfield id="NPUWRITE" description="Non Controller NPU Write Violation Flag" begin="12" end="12" width="1" rwaccess="R"/>
</register>
<register id="NMAVSET" width="32" page="1" offset="0x2" internal="0" description="Non-Controller Access Violation Flag Set Register">
<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag Set" begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag Set" begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag Set" begin="2" end="2" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag Set" begin="3" end="3" width="1" rwaccess="RW"/>
<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag Set" begin="4" end="4" width="1" rwaccess="RW"/>
<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag Set" begin="5" end="5" width="1" rwaccess="RW"/>
<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag Set" begin="6" end="6" width="1" rwaccess="RW"/>
<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag Set" begin="10" end="10" width="1" rwaccess="RW"/>
<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag Set" begin="11" end="11" width="1" rwaccess="RW"/>
<bitfield id="NPUWRITE" description="Non Controller NPU Write Access Violation Flag Set" begin="12" end="12" width="1" rwaccess="RW"/>
</register>
<register id="NMAVCLR" width="32" page="1" offset="0x4" internal="0" description="Non-Controller Access Violation Flag Clear Register">
<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag Clear " begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag Clear " begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag Clear " begin="2" end="2" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag Clear " begin="3" end="3" width="1" rwaccess="RW"/>
<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag Clear " begin="4" end="4" width="1" rwaccess="RW"/>
<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag Clear " begin="5" end="5" width="1" rwaccess="RW"/>
<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag Clear " begin="6" end="6" width="1" rwaccess="RW"/>
<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag Clear " begin="10" end="10" width="1" rwaccess="RW"/>
<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag Clear " begin="11" end="11" width="1" rwaccess="RW"/>
<bitfield id="NPUWRITE" description="Non Controller NPU Write Access Violation Flag Clear " begin="12" end="12" width="1" rwaccess="RW"/>
</register>
<register id="NMAVINTEN" width="32" page="1" offset="0x6" internal="0" description="Non-Controller Access Violation Interrupt Enable Register">
<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Interrupt Enable " begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Interrupt Enable " begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Interrupt Enable " begin="2" end="2" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Interrupt Enable " begin="3" end="3" width="1" rwaccess="RW"/>
<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Interrupt Enable " begin="4" end="4" width="1" rwaccess="RW"/>
<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Interrupt Enable " begin="5" end="5" width="1" rwaccess="RW"/>
<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Interrupt Enable " begin="6" end="6" width="1" rwaccess="RW"/>
<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Interrupt Enable " begin="10" end="10" width="1" rwaccess="RW"/>
<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Interrupt Enable " begin="11" end="11" width="1" rwaccess="RW"/>
<bitfield id="NPUWRITE" description="Non Controller NPU Write Violation Interrupt Enable " begin="12" end="12" width="1" rwaccess="RW"/>
</register>
<register id="NMCPURDAVADDR" width="32" page="1" offset="0x8" internal="0" description="Non-Controller CPU Read Access Violation Address">
<bitfield id="NMCPURDAVADDR" description="Non Controller CPU read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMCPUWRAVADDR" width="32" page="1" offset="0xa" internal="0" description="Non-Controller CPU Write Access Violation Address">
<bitfield id="NMCPUWRAVADDR" description="Non Controller CPU write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMCPUFAVADDR" width="32" page="1" offset="0xc" internal="0" description="Non-Controller CPU Fetch Access Violation Address">
<bitfield id="NMCPUFAVADDR" description="Non Controller CPU fetch access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMDMAWRAVADDR" width="32" page="1" offset="0xe" internal="0" description="Non-Controller DMA Write Access Violation Address">
<bitfield id="NMDMAWRAVADDR" description="Non Controller DMA write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMCLA1RDAVADDR" width="32" page="1" offset="0x10" internal="0" description="Non-Controller CLA1 Read Access Violation Address">
<bitfield id="NMCLA1RDAVADDR" description="Non Controller CLA1 read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMCLA1WRAVADDR" width="32" page="1" offset="0x12" internal="0" description="Non-Controller CLA1 Write Access Violation Address">
<bitfield id="NMCLA1WRAVADDR" description="Non Controller CLA1 write violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMCLA1FAVADDR" width="32" page="1" offset="0x14" internal="0" description="Non-Controller CLA1 Fetch Access Violation Address">
<bitfield id="NMCLA1FAVADDR" description="Non Controller CLA1 fetch violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMDMARDAVADDR" width="32" page="1" offset="0x1c" internal="0" description="Non-Controller DMA Read Access Violation Address">
<bitfield id="NMDMARDAVADDR" description="Non Controller DMA read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="MAVFLG" width="32" page="1" offset="0x20" internal="0" description="Controller Access Violation Flag Register">
<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag" begin="0" end="0" width="1" rwaccess="R"/>
<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag" begin="1" end="1" width="1" rwaccess="R"/>
<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag" begin="2" end="2" width="1" rwaccess="R"/>
</register>
<register id="MAVSET" width="32" page="1" offset="0x22" internal="0" description="Controller Access Violation Flag Set Register">
<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag Set" begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag Set" begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag Set" begin="2" end="2" width="1" rwaccess="RW"/>
</register>
<register id="MAVCLR" width="32" page="1" offset="0x24" internal="0" description="Controller Access Violation Flag Clear Register">
<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag Clear " begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag Clear " begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag Clear " begin="2" end="2" width="1" rwaccess="RW"/>
</register>
<register id="MAVINTEN" width="32" page="1" offset="0x26" internal="0" description="Controller Access Violation Interrupt Enable Register">
<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Interrupt Enable " begin="0" end="0" width="1" rwaccess="RW"/>
<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Interrupt Enable " begin="1" end="1" width="1" rwaccess="RW"/>
<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Interrupt Enable " begin="2" end="2" width="1" rwaccess="RW"/>
</register>
<register id="MCPUFAVADDR" width="32" page="1" offset="0x28" internal="0" description="Controller CPU Fetch Access Violation Address">
<bitfield id="MCPUFAVADDR" description="Controller CPU fetch access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="MCPUWRAVADDR" width="32" page="1" offset="0x2a" internal="0" description="Controller CPU Write Access Violation Address">
<bitfield id="MCPUWRAVADDR" description="Controller CPU write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="MDMAWRAVADDR" width="32" page="1" offset="0x2c" internal="0" description="Controller DMA Write Access Violation Address">
<bitfield id="MDMAWRAVADDR" description="Controller DMA write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMNPURDAVADDR" width="32" page="1" offset="0x3a" internal="0" description="Non-Controller NPU Read Access Violation Address">
<bitfield id="NMNPURDAVADDR" description="Non Controller NPU read violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
<register id="NMNPUWRAVADDR" width="32" page="1" offset="0x3c" internal="0" description="Non-Controller NPU Write Access Violation Address">
<bitfield id="NMNPUWRAVADDR" description="Non Controller NPU write violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
</register>
</module>
Loading