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Pull requests: diffblue/hw-cbmc

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Pull requests list

cleanup SVA sequence encoding cleanup engines Verilog
#1823 opened Apr 23, 2026 by kroening Collaborator Loading…
test to determine binding of else vs. if action blocks Tests Verilog
#1822 opened Apr 23, 2026 by kroening Collaborator Loading…
1
New IC3/PDR engine
#1817 opened Apr 21, 2026 by kroening Collaborator • Draft
Verilog: create $root module instance
#1816 opened Apr 21, 2026 by kroening Collaborator • Draft
use FPA theory when generating SMT-LIB2 for Z3 engines
#1812 opened Apr 20, 2026 by kroening Collaborator Loading…
3
Verilog: grammar for programs Verilog
#1811 opened Apr 18, 2026 by kroening Collaborator • Draft
Verilog: multiple top-level modules Verilog
#1807 opened Apr 17, 2026 by kroening Collaborator • Draft
netlist conversion: split up vector equality constraints engines
#1802 opened Apr 12, 2026 by kroening Collaborator • Draft
BDD model checker: early variable quantification
#1801 opened Apr 9, 2026 by kroening Collaborator • Draft
Verilog: $root Verilog
#1797 opened Apr 8, 2026 by kroening Collaborator • Draft
SystemVerilog: property-typed ports for checkers Verilog
#1739 opened Mar 18, 2026 by kroening Collaborator • Draft
class interface for flex
#1695 opened Mar 4, 2026 by kroening Collaborator • Draft
2
SystemVerilog: detect import conflicts Verilog
#1693 opened Mar 3, 2026 by kroening Collaborator • Draft
2
BDD engine: project away inputs engines
#1687 opened Mar 1, 2026 by kroening Collaborator • Draft
SystemVerilog queue benchmarks Tests Verilog
#1634 opened Feb 10, 2026 by kroening Collaborator • Draft
nondet elimination for AIGs engines
#1612 opened Feb 1, 2026 by kroening Collaborator • Draft
AIG simplifier using equivalences
#1605 opened Jan 26, 2026 by kroening Collaborator • Draft
1
bv_varidt now has next member engines
#1586 opened Jan 12, 2026 by kroening Collaborator • Draft
1
Verilog: use instance_array for width of primitive gates cleanup Verilog
#1501 opened Dec 20, 2025 by kroening Collaborator Loading…
1
SystemVerilog: sequence and property ports Verilog
#1436 opened Nov 24, 2025 by kroening Collaborator • Draft
Make the counter synthesizable, update comment
#1414 opened Nov 15, 2025 by ShashankVM Contributor • Draft
2
SMV: pre-traversal identifier conversion SMV
#1409 opened Nov 12, 2025 by kroening Collaborator • Draft
SMV output: use IVAR
#1396 opened Nov 9, 2025 by kroening Collaborator • Draft
netlist conversion: replace recursion by explicit stack engines
#1373 opened Oct 29, 2025 by kroening Collaborator • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening Collaborator • Draft
ProTip! Updated in the last three days: updated:>2026-04-20.