feat(c-prime-rtl): LOAD-PHYS-CONST 0xDE hardware hook · L-DPC24 Lane C'

[gHashTag]

LOAD-PHYS-CONST 0xDE — RTL Hook · L-DPC24 Lane C'

Ref: gHashTag/trinity-fpga#99
Paired ISA spec PR: gHashTag/t27#632

What this PR does

Adds the SystemVerilog RTL hook for the LDPC (LOAD-PHYS-CONST) instruction, opcode 0xDE. This is a 1-cycle registered ROM-read module implementing the 75-cell Sacred ROM.

Files added

• rtl/holo_load_phys_const.sv — RTL implementation
• rtl/holo_load_phys_const_tb.sv — Testbench (3 test cases)

Module interface

module holo_load_phys_const #(
    parameter int unsigned ROM_DEPTH = 75,
    parameter int unsigned DATA_W    = 64
) (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        valid_i,
    input  wire [6:0]  imm7_i,
    output logic       valid_o,
    output logic [63:0] data_o,
    output logic       oob_o       // 1 when imm7 >= 75
);

• default_nettype none, no * operators
• 1-cycle registered ROM read
• oob_o=1 when imm7 >= 75 (ISA UB region)

Sacred ROM (PLACEHOLDER — R18 LAYER-FROZEN)

Cell	Constant	Sentinel	Status
0	φ	64hDEAD_0000_C0DE_000164hDEAD_0000_C0DE_0002	placeholder ← Lane E' P3
2	C=φ⁻¹	64hDEAD_0000_C0DE_000364hDEAD_0000_C0DE_0004	placeholder ← Lane E' P3
4–74	reserved	64'h0	placeholder

R18 LAYER-FROZEN: All ROM cells are symbolic placeholders. Replace with Lane E' P3 frozen-hash-validated constants before tapeout.

Testbench coverage

Test	Input	Expected	Description
1	imm7=0	valid_o=1, oob_o=0, data_o≠0	Load φ placeholder
2	imm7=74	valid_o=1, oob_o=0	Last valid cell
3	imm7=75	oob_o=1, data_o=0	First UB cell

R5-HONEST verdict

RTL structurally clean (interface correct, 1-cycle path, OOB guard present).
Simulation status: Unknown — CI verifies. ROM constants are placeholders.

Anchor

φ²+φ⁻²=3