feat(t): Wave-30 Lane T — 400 MHz timing-closure probe (🟡 SYNTH-SIM)

[gHashTag]

Wave-30 Lane T — 400 MHz Timing-Closure Probe

Verdict: 🟡 SYNTH-SIM — constraint-only addition, no RTL modified.

What this PR does

Adds a synthesis timing-closure probe for the 4 merged RTL surfaces (Lane V LUT PE, Lane W BitROM bank, Lane V' 2×2 mesh, Lane S Sparsity 2:4) under a 400 MHz (2.5 ns) target clock, using Yosys + OpenSTA against sky130 HD as a TTIHP27a-class proxy.

Files added

File	Description
sim/timing_probe_400mhz/Makefile	Yosys synth + OpenSTA STA orchestration; targets yosys, report, clean
sim/timing_probe_400mhz/constraints.sdc	2.5 ns clock, 0.5 ns I/O delays, set_max_fanout 10, set_load 0.001
sim/timing_probe_400mhz/report.md	🟡 SYNTH-SIM skeleton with per-surface slack table; populated by make report
docs/lever-stack/lane-t.md	Pre-registration H_W30-T, method, R-rules attestation matrix, 3 falsification witnesses

R-rules

Rule	Status
R-SI-1 (ZERO * in RTL)	N/A — zero RTL added
R18 LAYER-FROZEN (no RTL from PRs #19/#14/#21/#26 modified)	✅ PASS — git diff main -- rtl/ = 0 lines
R5-HONEST (🟡 SYNTH-SIM label)	✅ PASS — Yosys-vs-commercial-STA gap disclosed in report.md, Makefile header, and lane-t.md

Commercial-STA gate

This probe uses sky130 HD as a ±15–20% proxy. Commercial-STA sign-off (PrimeTime / Tempus + TTIHP27a Liberty) is gated on TTIHP27a return 2026-09-30.

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Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

Refs #109

Signed-off-by: Vasilev Dmitrii admin@t27.ai