Fix ch32v103 hardfault & Add CH32V103C8T6 Bluepill board

[UMRnInside]

compile but does not run (no blinky), probably due to compile/linker/startup issue

#2674 has a startup issue in board_init() : __disable_irq() from CH32V103 EVT calls csrc mstatus, 0x88 in U-mode (which is only allowed in M-mode)

https://github.com/openwch/ch32v103/blob/f99a84c4c42b6fb676560a9b8b7c737401efe0ad/EVT/EXAM/SRC/Core/core_riscv.h#L144-L155

__disable_irq() in CH32V307 EVT (probably also in CH32V203), however, uses vendor-defined CSR 0x800. This CSR is writable in U-mode, according to QingKeV3 Processor Manual:

https://github.com/openwch/ch32v307/blob/7e33c66cd91008054d2a37db534b10162d1f0c6e/EVT/EXAM/SRC/Core/core_riscv.h#L141-L145

Now you can see the LED blinking, log outputting from UART(if LOG=2), but cdc_msc example is still not working.

USBD init on controller 0, speed = Auto
sizeof(usbd_device_t) = 55
sizeof(dcd_event_t) = 12
sizeof(tu_fifo_t) = 12
sizeof(tu_edpt_stream_t) = 24
CDC init
MSC init
sizeof(mscd_interface_t) = 64
USBD Bus Reset : Full Speed

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...