Skip to content

Pull requests: llvm/circt

New pull request New
210 Open 7,366 Closed
210 Open 7,366 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

ImportVerilog: improve testbench compatibility
#10095 opened Apr 1, 2026 by AmurG Loading…
[ImportVerilog] Add capture analysis pre-pass for functions ImportVerilog
#10094 opened Apr 1, 2026 by fabianschuiki Loading…
4
[FIRRTL][OM] Add property asserts
#10093 opened Apr 1, 2026 by seldridge • Draft
1
[ImportVerilog] Support case inside statements
#10090 opened Mar 31, 2026 by sunhailong2001 Loading…
2
[Arc][Conversion] Lower sim.clocked_terminate to exit in LowerArcToLLVM Arc Involving the `arc` dialect
#10089 opened Mar 31, 2026 by nanjo712 Loading…
1
6
[circt-bmc] Preserve signal names before lowering
#10075 opened Mar 29, 2026 by ankit-cybertron Loading…
15
[Synth] [FunctionalReduction] Add conflict limit option, and add to circt-synth
#10073 opened Mar 28, 2026 by uenoku Loading…
[circt-reduce] Add domain field remover
#10062 opened Mar 27, 2026 by seldridge • Draft
1
[circt-bmc] Include bound in violation and success messages
#10056 opened Mar 26, 2026 by AnmolM-777 Loading…
1
[circt-bmc] Include bound in violation and success messages
#10051 opened Mar 26, 2026 by AnmolM-777 Loading…
2
Conditonally add external attribute for memory element
#10050 opened Mar 26, 2026 by Abhilekhgautam Loading…
1
3
Bump LLVM to 80603c6672226cb48798bd60120c8f859dbeca19.
#10047 opened Mar 26, 2026 by mikeurbach Loading…
11
[FIRRTL] Improve domain port naming in InferDomains pass
#10037 opened Mar 25, 2026 by seldridge • Draft
[ExportVerilog] Add ModportType support for non-extern hw.module ports
#10030 opened Mar 25, 2026 by dmlockhart Loading…
5
[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)
#10025 opened Mar 24, 2026 by Salmooo Loading…
12
[FIRRTL] Invalids as constants in InferDomains
#10022 opened Mar 24, 2026 by seldridge • Draft
1
[HW] Add IMDCE module rewrites
#10007 opened Mar 22, 2026 by stomfaig Loading…
6
[HWFlattenModules] Add support for verif.formal parent ops.
#9984 opened Mar 19, 2026 by dobios • Draft
2
[RTG][circt-tblgen] Use config vars for include paths RTG Involving the `rtg` dialect
#9982 opened Mar 19, 2026 by maerhart Loading…
1
1
[Handshake] Fix argument index tracking with multiple ext memref args
#9978 opened Mar 19, 2026 by TopiLeppanen Loading…
1
[Sim][SimToSv] DPI-C Semantic preserving sim.func.dpi and sim.func.dpi.call
#9977 opened Mar 19, 2026 by pscabot Loading…
20
[FIRRTL] Emit memory initialization metadata FIRRTL Involving the `firrtl` dialect
#9974 opened Mar 18, 2026 by fzi-hielscher Loading…
1
[Datapath] Implement Add with Carry-In to Improve Subtraction Circuit Implementation
#9949 opened Mar 16, 2026 by sarthakmangla1 • Draft
1 task
8
[ImportVerilog][Sim] Added remaining Moore instructions for dynamic arrays, as well as the corresponding Sim dialect instructions
#9944 opened Mar 15, 2026 by yuriyKulinchenko Loading…
1
[FIRRTLToHW] Fix crash when lowering instance_choice with clock outputs
#9941 opened Mar 14, 2026 by seldridge • Draft
3
ProTip! Exclude everything labeled bug with -label:bug.