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Test Mat's Win/ARM64 PR5 alone#59

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swesonga wants to merge 2 commits intomacarte/baselinePR-TestTrampolineFixfrom
swesonga/PR5-winarm64
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Test Mat's Win/ARM64 PR5 alone#59
swesonga wants to merge 2 commits intomacarte/baselinePR-TestTrampolineFixfrom
swesonga/PR5-winarm64

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Determine what fails without PRs 1, 2, 3, and 4.

macarte and others added 2 commits March 16, 2026 11:31
…alThread

On ARM64, volatile write (STLR/release) + volatile read (LDAR/acquire) to
different addresses does NOT provide StoreLoad ordering. This breaks
Dekker-like protocols where one side writes field A then reads field B,
while the other writes B then reads A — both sides can miss each other's
stores.

This adds U.fullFence() / VarHandle.fullFence() at all identified
Dekker-pattern sites:

VirtualThread.java:
  - afterYield() PARKING path: between setState(PARKED/TIMED_PARKED) and
    reading parkPermit (Dekker with unpark)
  - afterYield() BLOCKING path: between setState(BLOCKED) and reading
    blockPermit (Dekker with unblock)
  - afterYield() WAITING path: between setState(WAIT/TIMED_WAIT) and
    reading notified (Dekker with notify); fences in both untimed and
    timed sub-paths (adapted for tip's per-path inline checks)
  - afterDone(): between setState(TERMINATED) and reading
    notifyAllAfterTerminate (Dekker with beforeJoin)
  - unpark(): between getAndSetParkPermit(true) and reading state
    (Dekker with afterYield PARKING path)
  - unblock(): between blockPermit=true and reading state (Dekker with
    afterYield BLOCKING path)

LinkedTransferQueue.java:
  - xfer(): between cmpExItem CAS and reading waiter (Dekker with
    await() which writes waiter then reads item)

SynchronousQueue.java:
  - xferLifo(): between cmpExItem CAS and reading waiter (same Dekker
    as LinkedTransferQueue)

AbstractQueuedSynchronizer.java:
  - acquire(): between node.status=WAITING and re-reading state in
    tryAcquire/tryAcquireShared (Dekker with release/releaseShared)
  - release(): between tryRelease state update and reading node.status
    in signalNext
  - releaseShared(): same as release()

These fences are correctness-critical on ARM64, functionally redundant
on x86 (TSO already provides StoreLoad), and appear only on non-hot
paths (state transitions, not tight loops).
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2 participants