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| // We need to mark the line dirty if it's write. | ||
| // Metadata & 0x2 == dirty, and metadata 0x1 == valid. Map to those. | ||
| if (request->type == VR4300_BUS_REQUEST_READ_CONDITIONAL) |
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shouldn't this be checking for VR4300_BUS_REQUEST_STORE_CONDITIONAL?
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I think this block may be dedup'd with the original store/load path, replacing this if statement with:
line->metadata |= (exdc_latch->request.type & 0x3);
and carefully picking constant vals for VR4300_BUS_REQUEST_READ_CONDITIONAL and VR4300_BUS_REQUEST_WRITE_CONDITIONAL.
| return 0; // fail is not an exception | ||
| } else { | ||
| // Successful store, set the reg to 1 | ||
| vr4300->regs[exdc_latch->request.sc_reg] = 1; |
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Should this be a pipelined write? Otherwise, the result may not be correctly forwarded:
https://github.com/n64dev/cen64/blob/master/vr4300/pipeline.c#L173
dcwb_latch->dest = exdc_latch->request.sc_reg;
dcwb_latch->result = 1
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Read conditional seems like it would create LDIs as well: |
| vr4300->regs[VR4300_CP0_REGISTER_LLADDR] != paddr >> 4) { | ||
| // Fail the store, set the reg to 0, write nothing to memory | ||
| exdc_latch->request.type = VR4300_BUS_REQUEST_NONE; | ||
| vr4300->regs[exdc_latch->request.sc_reg] = 0; |
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Must be written by WB for forwarding:
dcwb_latch->dest = exdc_latch->request.sc_reg;
dcwb_latch->result = 0;
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Thanks for the quick review.
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ahh okay, yes, you're correct - I had thought it was reversed. |
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