pulp-platform · smanoni · Mar 11, 2026 · Mar 11, 2026 · Mar 12, 2026 · Apr 8, 2026
diff --git a/.gitmodules b/.gitmodules
@@ -69,7 +69,8 @@
 	url = https://github.com/pulp-platform/icache-intc.git
 [submodule "hw/ips/jtag_pulp"]
 	path = hw/ips/jtag_pulp
-	url = https://github.com/pulp-platform/jtag_pulp.git
+	url = git@github.com:smanoni/jtag_pulp.git
+	branch = sm/lint
 [submodule "hw/ips/l2_tcdm_hybrid_interco"]
 	path = hw/ips/l2_tcdm_hybrid_interco
 	url = https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
@@ -99,7 +100,8 @@
 	url = git@github.com:pulp-platform/tech_cells_generic.git
 [submodule "hw/ips/timer_unit"]
 	path = hw/ips/timer_unit
-	url = https://github.com/pulp-platform/timer_unit.git
+	url = git@github.com:smanoni/timer_unit.git
+	branch = sm/cp-lint
 [submodule "hw/ips/udma_core"]
 	path = hw/ips/udma_core
 	url = https://github.com/pulp-platform/udma_core.git

diff --git a/Bender.yml b/Bender.yml
@@ -36,7 +36,7 @@ dependencies:
   wdt: { path: "hw/ips/wdt" }
   axi2mem: { path: "hw/ips/axi2mem" }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
-  jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.3.0 }
+  jtag_pulp: { git: "git@github.com:smanoni/jtag_pulp.git", rev: "sm/lint" }
   idma: { git: "https://github.com/pulp-platform/idma.git", rev: 5af5d10 }
   pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "control-pulp" }
   pulp_cluster: { git: "https://github.com/pulp-platform/pulp_cluster.git", rev: "control-pulp" }

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,6 +4,30 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 ## Unreleased
+## [5.5.0] - 2026-05-20
+### DARE v2.3 Release
+### Changed
+- Updated `hw/ips/common_cells` dependency to the latest version (v2.1).
+- Removed dependencies on deprecated `common_cells` modules (`system_clk_rst_gen.sv`).
+- Updated `hw/ips/cv32e40p`, `hw/ips/cluster_interconnect`, and `hw/ips/udma_filter`
+  to fix linting warnings WRN_62, WRN_64, SYNTH_89, SYNTH_5143, SYNTH_12605, SYNTH_5166 and SYNTH_5064.
+- Added proper assertion guards in `hw/ips/cv32e40p`, `hw/ips/cluster_interconnect`,
+  and `hw/ips/udma_filter`.
+
+## [5.4.0] - 2026-02-12
+### DARE v2.2 Release
+### Added
+- Lint flow based on Slang and Spyglass
+
+### Changed
+- Updated tc_sram dependency (memory macros sim-only models) to avoid
+  unsythesizable errors in Spyglass. pragma translate on/off has been 
+  added to the whole module resulting in 'empty module' error, to be waived
+  in linting, to be properly addressed during backend.
+- Updated SIM_STDOUT default param of pms_top to 0, to avoid instantiation of tbs
+  in Spyglass where is not possible to drive top-level parameters externally.
+- Exposed testmode_i of axi_to_reg instance in axi_scmi_mailbox module. Tied 
+  it to zero in control_pulp_fpga, as currently DFT is disabled in our FPGA platform.
 
 ## [5.3.0] - 2022-04-07
 ### Added

diff --git a/Makefile b/Makefile
@@ -80,7 +80,7 @@ $(export_if_def VERILATOR)
 $(export_if_def QUESTA)
 
 NONFREE_REMOTE = git@iis-git.ee.ethz.ch:pms/control-pulp-nonfree.git
-NONFREE_COMMIT = ee818ec
+NONFREE_COMMIT = f14a2b58
 
 .PHONY: nonfree-init
 nonfree-init:
@@ -140,7 +140,7 @@ gen: update-serial-link
 	sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' sim/gen/sim.f
 
 # Verilator
-	$(BENDER) script verilator $(BENDER_BASE_TARGETS) > sim/gen/veri.f
+	$(BENDER) script verilator $(BENDER_BASE_TARGETS) -D ASSERTS_OFF > sim/gen/veri.f
 	sed -i 's?$(ROOT_DIR)?\$$ROOT?g' sim/gen/veri.f
 	sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' sim/gen/veri.f
 
@@ -330,7 +330,7 @@ SG_DIR  ?= $(ROOT_DIR)/util/lint/spyglass
 # Remove axi_cdc.sv coming from axi_slice_dc directory to void duplicate module definitions
 gen_sg_script:
 	mkdir -p $(SG_DIR)
-	$(BENDER) script verilator $(BENDER_BASE_TARGETS) -D SYNTHESIS > $(SG_DIR)/cp_sg.f
+	$(BENDER) script verilator $(BENDER_BASE_TARGETS) -D SYNTHESIS -D ASSERTS_OFF -D COMMON_CELLS_ASSERTS_OFF > $(SG_DIR)/cp_sg.f
 	sed -i 's?$(ROOT_DIR)?\$$CPROOT?g' $(SG_DIR)/cp_sg.f
 	sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' $(SG_DIR)/cp_sg.f
 

diff --git a/hw/includes/cluster_bus_defines.sv b/hw/includes/cluster_bus_defines.sv
@@ -19,10 +19,10 @@
 
 // CLUSTER BUS PARAMETRES
 
-`define NB_SLAVE  4
-`define NB_MASTER 3
+`define CLUSTER_BUS_NB_SLAVE  4
+`define CLUSTER_BUS_NB_MASTER 3
 
-`define NB_REGION 1
+`define CLUSTER_BUS_NB_REGION 1
 
 // MSTER PORT TO TCDM
 `define MASTER_0_START_ADDR 32'h1000_0000

diff --git a/hw/includes/instr_bus_defines.sv b/hw/includes/instr_bus_defines.sv
@@ -20,7 +20,7 @@
 // INSTRUCTION BUS PARAMETRES
 
 // L2
-`define NB_REGION 2
+`define INSTR_BUS_NB_REGION 2
 
 `define MASTER_0_REGION_0_START_ADDR 32'h1A00_0000
 `define MASTER_0_REGION_0_END_ADDR   32'h1DFF_FFFF

diff --git a/hw/includes/soc_bus_defines.sv b/hw/includes/soc_bus_defines.sv
@@ -17,9 +17,9 @@
 // SOC BUS PARAMETRES
 `include "pulp_soc_defines.sv"
 
-`define NB_SLAVE  4
-`define NB_MASTER 4
-`define NB_REGION 4
+`define SOC_BUS_NB_SLAVE  4
+`define SOC_BUS_NB_MASTER 4
+`define SOC_BUS_NB_REGION 4
 
 // MASTER PORT TO CLUSTER(3MB)
 `define CLUSTER_DATA_START_ADDR  32'h1000_0000

diff --git a/hw/ips/axi b/hw/ips/axi
diff --git a/hw/ips/cluster_interconnect b/hw/ips/cluster_interconnect
diff --git a/hw/ips/cluster_peripherals b/hw/ips/cluster_peripherals
diff --git a/hw/ips/common_cells b/hw/ips/common_cells
diff --git a/hw/ips/cv32e40p b/hw/ips/cv32e40p
diff --git a/hw/ips/event_unit_flex b/hw/ips/event_unit_flex
diff --git a/hw/ips/idma b/hw/ips/idma
diff --git a/hw/ips/jtag_pulp b/hw/ips/jtag_pulp
diff --git a/hw/ips/pulp_cluster b/hw/ips/pulp_cluster
diff --git a/hw/ips/timer_unit b/hw/ips/timer_unit
diff --git a/hw/ips/udma_filter b/hw/ips/udma_filter
diff --git a/hw/ips/udma_i2c b/hw/ips/udma_i2c
diff --git a/hw/ips/udma_qspi b/hw/ips/udma_qspi
diff --git a/hw/ips/udma_uart b/hw/ips/udma_uart
diff --git a/hw/pulp/control_pulp.sv b/hw/pulp/control_pulp.sv
@@ -203,7 +203,7 @@ module control_pulp import control_pulp_pkg::*; #(
   localparam int unsigned AXI_CLUSTER_SOC_DATA_WIDTH = 64;
   localparam int unsigned AXI_SOC_CLUSTER_DATA_WIDTH = 32;
   localparam int unsigned AXI_SOC_CLUSTER_ID_WIDTH   = pkg_soc_interconnect::AXI_ID_OUT_WIDTH; // = 1 + clog2(13) = 5
-  localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH   = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`NB_SLAVE); // = 5 + clog2(4) = 7;
+  localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH   = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`SOC_BUS_NB_SLAVE); // = 5 + clog2(4) = 7;
 
   localparam int unsigned AXI_USER_WIDTH             = 6;
   localparam int unsigned AXI_CLUSTER_SOC_STRB_WIDTH = AXI_CLUSTER_SOC_DATA_WIDTH/8;

diff --git a/hw/pulp/system_clk_rst_gen.sv b/hw/pulp/system_clk_rst_gen.sv
@@ -89,16 +89,19 @@ module system_clk_rst_gen (
 
   // ref_clk -> divider -> 32 Khz timer clock
   // fixed division by integer factor
-  clk_div #(
-    .RATIO(3125)  // TODO: ADJUST RATIO to match ref clk
-                  // 100 Mhz / 32 Khz = 3125
-  ) i_clk_div_timer (
-    .clk_i     (ref_clk_i),
-    .rst_ni    (rstn_glob_i),
-    .testmode_i(test_mode_i),
-    .en_i      (1'b1),           // TODO: maybe we can map this to reg
-    .clk_o     (clk_for_slow)
-  );
+  clk_int_div #(
+    .DIV_VALUE_WIDTH($clog2(3125+1)),
+    .DEFAULT_DIV_VALUE(3125)
+  ) i_clk_div_timer(
+    .clk_i           ( ref_clk_i    ),
+    .rst_ni          ( rstn_glob_i  ),
+    .test_mode_en_i  ( test_mode_i  ),
+    .en_i            ( 1'b1         ), // TODO: maybe we can map this to reg 
+    .div_i           (  '1          ),
+    .div_valid_i     ( 1'b0         ),
+    .div_ready_o     (              ),
+    .clk_o           ( clk_for_slow )
+  ); 
 
   // Allow clock muxing if dividers are faulty: ref_clk passthrough
   pulp_clock_mux2 i_clk_mux_soc (

diff --git a/sim/gen/sim.f b/sim/gen/sim.f
@@ -19,14 +19,14 @@
 +incdir+$CPROOT/hw/ips/udma_core/rtl
 +incdir+$CPROOT/hw/ips/udma_i2c/rtl
 +incdir+$CPROOT/hw/ips/udma_qspi/rtl
-+define+CV32E40P_TRACE_EXECUTION
-+define+TARGET_SIMULATION
-+define+TRACE_EXECUTION
 +define+TARGET_CV32E40P_USE_FF_REGFILE
 +define+TARGET_FLIST
 +define+TARGET_PULP
 +define+TARGET_RTL
++define+TARGET_SIMULATION
 +define+TARGET_TEST
++define+CV32E40P_TRACE_EXECUTION
++define+TRACE_EXECUTION
 $CPROOT/hw/ips/common_verification/src/clk_rst_gen.sv
 $CPROOT/hw/ips/common_verification/src/rand_id_queue.sv
 $CPROOT/hw/ips/common_verification/src/rand_stream_mst.sv
@@ -55,23 +55,29 @@
 $CPROOT/hw/ips/common_cells/src/binary_to_gray.sv
 $CPROOT/hw/ips/common_cells/src/cb_filter_pkg.sv
 $CPROOT/hw/ips/common_cells/src/cc_onehot.sv
+$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr_pkg.sv
 $CPROOT/hw/ips/common_cells/src/cf_math_pkg.sv
 $CPROOT/hw/ips/common_cells/src/clk_int_div.sv
+$CPROOT/hw/ips/common_cells/src/credit_counter.sv
 $CPROOT/hw/ips/common_cells/src/delta_counter.sv
 $CPROOT/hw/ips/common_cells/src/ecc_pkg.sv
 $CPROOT/hw/ips/common_cells/src/edge_propagator_tx.sv
 $CPROOT/hw/ips/common_cells/src/exp_backoff.sv
 $CPROOT/hw/ips/common_cells/src/fifo_v3.sv
 $CPROOT/hw/ips/common_cells/src/gray_to_binary.sv
+$CPROOT/hw/ips/common_cells/src/heaviside.sv
 $CPROOT/hw/ips/common_cells/src/isochronous_4phase_handshake.sv
 $CPROOT/hw/ips/common_cells/src/isochronous_spill_register.sv
 $CPROOT/hw/ips/common_cells/src/lfsr.sv
 $CPROOT/hw/ips/common_cells/src/lfsr_16bit.sv
 $CPROOT/hw/ips/common_cells/src/lfsr_8bit.sv
+$CPROOT/hw/ips/common_cells/src/lossy_valid_to_stream.sv
 $CPROOT/hw/ips/common_cells/src/mv_filter.sv
 $CPROOT/hw/ips/common_cells/src/onehot_to_bin.sv
 $CPROOT/hw/ips/common_cells/src/plru_tree.sv
+$CPROOT/hw/ips/common_cells/src/passthrough_stream_fifo.sv
 $CPROOT/hw/ips/common_cells/src/popcount.sv
+$CPROOT/hw/ips/common_cells/src/ring_buffer.sv
 $CPROOT/hw/ips/common_cells/src/rr_arb_tree.sv
 $CPROOT/hw/ips/common_cells/src/rstgen_bypass.sv
 $CPROOT/hw/ips/common_cells/src/serial_deglitch.sv
@@ -82,21 +88,26 @@
 $CPROOT/hw/ips/common_cells/src/stream_filter.sv
 $CPROOT/hw/ips/common_cells/src/stream_fork.sv
 $CPROOT/hw/ips/common_cells/src/stream_intf.sv
-$CPROOT/hw/ips/common_cells/src/stream_join.sv
+$CPROOT/hw/ips/common_cells/src/stream_join_dynamic.sv
 $CPROOT/hw/ips/common_cells/src/stream_mux.sv
 $CPROOT/hw/ips/common_cells/src/stream_throttle.sv
 $CPROOT/hw/ips/common_cells/src/sub_per_hash.sv
 $CPROOT/hw/ips/common_cells/src/sync.sv
 $CPROOT/hw/ips/common_cells/src/sync_wedge.sv
 $CPROOT/hw/ips/common_cells/src/unread.sv
 $CPROOT/hw/ips/common_cells/src/read.sv
-$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr_pkg.sv
-$CPROOT/hw/ips/common_cells/src/addr_decode_napot.sv
+$CPROOT/hw/ips/common_cells/src/addr_decode_dync.sv
+$CPROOT/hw/ips/common_cells/src/boxcar.sv
 $CPROOT/hw/ips/common_cells/src/cdc_2phase.sv
 $CPROOT/hw/ips/common_cells/src/cdc_4phase.sv
+$CPROOT/hw/ips/common_cells/src/clk_int_div_static.sv
+$CPROOT/hw/ips/common_cells/src/trip_counter.sv
 $CPROOT/hw/ips/common_cells/src/addr_decode.sv
+$CPROOT/hw/ips/common_cells/src/addr_decode_napot.sv
+$CPROOT/hw/ips/common_cells/src/multiaddr_decode.sv
 $CPROOT/hw/ips/common_cells/src/cb_filter.sv
 $CPROOT/hw/ips/common_cells/src/cdc_fifo_2phase.sv
+$CPROOT/hw/ips/common_cells/src/clk_mux_glitch_free.sv
 $CPROOT/hw/ips/common_cells/src/counter.sv
 $CPROOT/hw/ips/common_cells/src/ecc_decode.sv
 $CPROOT/hw/ips/common_cells/src/ecc_encode.sv
@@ -108,7 +119,7 @@
 $CPROOT/hw/ips/common_cells/src/stream_delay.sv
 $CPROOT/hw/ips/common_cells/src/stream_fifo.sv
 $CPROOT/hw/ips/common_cells/src/stream_fork_dynamic.sv
-$CPROOT/hw/ips/common_cells/src/clk_mux_glitch_free.sv
+$CPROOT/hw/ips/common_cells/src/stream_join.sv
 $CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr.sv
 $CPROOT/hw/ips/common_cells/src/cdc_fifo_gray.sv
 $CPROOT/hw/ips/common_cells/src/fall_through_register.sv
@@ -120,9 +131,10 @@
 $CPROOT/hw/ips/common_cells/src/stream_xbar.sv
 $CPROOT/hw/ips/common_cells/src/cdc_fifo_gray_clearable.sv
 $CPROOT/hw/ips/common_cells/src/cdc_2phase_clearable.sv
-$CPROOT/hw/ips/common_cells/src/mem_to_banks.sv
+$CPROOT/hw/ips/common_cells/src/mem_to_banks_detailed.sv
 $CPROOT/hw/ips/common_cells/src/stream_arbiter.sv
 $CPROOT/hw/ips/common_cells/src/stream_omega_net.sv
+$CPROOT/hw/ips/common_cells/src/mem_to_banks.sv
 $CPROOT/hw/ips/common_cells/src/deprecated/sram.sv
 $CPROOT/hw/ips/common_cells/test/addr_decode_tb.sv
 $CPROOT/hw/ips/common_cells/test/cb_filter_tb.sv
@@ -133,6 +145,7 @@
 $CPROOT/hw/ips/common_cells/test/fifo_tb.sv
 $CPROOT/hw/ips/common_cells/test/graycode_tb.sv
 $CPROOT/hw/ips/common_cells/test/id_queue_tb.sv
+$CPROOT/hw/ips/common_cells/test/passthrough_stream_fifo_tb.sv
 $CPROOT/hw/ips/common_cells/test/popcount_tb.sv
 $CPROOT/hw/ips/common_cells/test/rr_arb_tree_tb.sv
 $CPROOT/hw/ips/common_cells/test/stream_test.sv
@@ -143,7 +156,9 @@
 $CPROOT/hw/ips/common_cells/test/stream_omega_net_tb.sv
 $CPROOT/hw/ips/common_cells/test/stream_xbar_tb.sv
 $CPROOT/hw/ips/common_cells/test/clk_int_div_tb.sv
+$CPROOT/hw/ips/common_cells/test/clk_int_div_static_tb.sv
 $CPROOT/hw/ips/common_cells/test/clk_mux_glitch_free_tb.sv
+$CPROOT/hw/ips/common_cells/test/lossy_valid_to_stream_tb.sv
 $CPROOT/hw/ips/common_cells/src/deprecated/clock_divider_counter.sv
 $CPROOT/hw/ips/common_cells/src/deprecated/clk_div.sv
 $CPROOT/hw/ips/common_cells/src/deprecated/find_first_one.sv
@@ -428,7 +443,6 @@
 $CPROOT/hw/ips/axi_slice_dc/src/dc_token_ring.v
 $CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_master_wrap.sv
 $CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_slave_wrap.sv
-$CPROOT/hw/ips/axi_slice_dc/src/axi_cdc.sv
 $CPROOT/hw/ips/clic/src/clic_reg_pkg.sv
 $CPROOT/hw/ips/clic/src/clic_reg_top.sv
 $CPROOT/hw/ips/clic/src/clic_reg_adapter.sv
@@ -761,6 +775,7 @@
 $CPROOT/hw/ips/pulp_soc/rtl/components/glitch_free_clk_mux.sv
 $CPROOT/hw/ips/pulp_soc/rtl/components/tcdm_arbiter_2x1.sv
 $CPROOT/hw/ips/pulp_soc/rtl/components/obi_pulp_adapter.sv
+$CPROOT/hw/ips/pulp_soc/rtl/components/glitch_free_clk_mux.sv
 $CPROOT/hw/ips/pulp_soc/rtl/components/apb_dummy.sv
 $CPROOT/hw/ips/pulp_soc/rtl/components/freq_meter.sv
 $CPROOT/hw/ips/serial_link/src/regs/serial_link_reg_pkg.sv
+25 −29		icache_ctrl_unit/icache_ctrl_unit.sv
+21 −26		icache_ctrl_unit/mp_icache_ctrl_unit.sv
+36 −42		icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv
+20 −23		icache_ctrl_unit/new_icache_ctrl_unit.sv
+21 −22		icache_ctrl_unit/pri_icache_ctrl_unit.sv
+44 −49		icache_ctrl_unit/sp_icache_ctrl_unit.sv
+5 −1		.gitlab-ci.yml
+94 −74		Bender.yml
+108 −0		CHANGELOG.md
+146 −131		README.md
+21 −4		common_cells.core
+86 −71		include/common_cells/assertions.svh
+23 −0		include/common_cells/registers.svh
+4 −4		lint/common_cells.style.waiver
+28 −101		src/addr_decode.sv
+177 −0		src/addr_decode_dync.sv
+5 −4		src/addr_decode_napot.sv
+31 −0		src/boxcar.sv
+8 −10		src/cb_filter.sv
+2 −2		src/cdc_2phase.sv
+6 −11		src/cdc_2phase_clearable.sv
+6 −6		src/cdc_fifo_2phase.sv
+10 −9		src/cdc_fifo_gray.sv
+9 −9		src/cdc_fifo_gray_clearable.sv
+9 −3		src/cf_math_pkg.sv
+56 −13		src/clk_int_div.sv
+95 −0		src/clk_int_div_static.sv
+79 −16		src/clk_mux_glitch_free.sv
+57 −0		src/credit_counter.sv
+10 −1		src/delta_counter.sv
+2 −3		src/deprecated/clk_div.sv
+0 −3		src/deprecated/clock_divider.sv
+3 −3		src/deprecated/fifo_v2.sv
+2 −2		src/deprecated/find_first_one.sv
+2 −2		src/deprecated/generic_fifo.sv
+2 −2		src/deprecated/generic_fifo_adv.sv
+7 −12		src/exp_backoff.sv
+4 −3		src/fall_through_register.sv
+9 −13		src/fifo_v3.sv
+25 −0		src/heaviside.sv
+46 −46		src/id_queue.sv
+6 −7		src/isochronous_4phase_handshake.sv
+7 −12		src/isochronous_spill_register.sv
+14 −19		src/lfsr.sv
+5 −7		src/lfsr_16bit.sv
+4 −6		src/lfsr_8bit.sv
+139 −0		src/lossy_valid_to_stream.sv
+19 −25		src/lzc.sv
+35 −131		src/mem_to_banks.sv
+233 −0		src/mem_to_banks_detailed.sv
+152 −0		src/multiaddr_decode.sv
+5 −6		src/onehot_to_bin.sv
+124 −0		src/passthrough_stream_fifo.sv
+28 −18		src/plru_tree.sv
+18 −38		src/popcount.sv
+175 −0		src/ring_buffer.sv
+28 −55		src/rr_arb_tree.sv
+4 −4		src/rstgen_bypass.sv
+1 −1		src/shift_reg_gated.sv
+6 −8		src/spill_register_flushable.sv
+3 −3		src/stream_arbiter_flushable.sv
+1 −1		src/stream_delay.sv
+6 −6		src/stream_fifo_optimal_wrap.sv
+4 −6		src/stream_fork.sv
+4 −6		src/stream_fork_dynamic.sv
+5 −5		src/stream_intf.sv
+9 −11		src/stream_join.sv
+45 −0		src/stream_join_dynamic.sv
+6 −8		src/stream_mux.sv
+31 −26		src/stream_omega_net.sv
+2 −2		src/stream_register.sv
+12 −12		src/stream_to_mem.sv
+24 −22		src/stream_xbar.sv
+51 −0		src/trip_counter.sv
+5 −1		src/unread.sv
+14 −3		src_files.yml
+7 −1		test/cdc_2phase_clearable_tb.sv
+1 −1		test/cdc_2phase_tb.sv
+1 −1		test/cdc_fifo_tb.sv
+88 −0		test/clk_int_div_static_tb.sv
+5 −5		test/clk_int_div_tb.sv
+2 −3		test/clk_mux_glitch_free_tb.sv
+3 −0		test/fifo_tb.sv
+109 −0		test/lossy_valid_to_stream_tb.sv
+135 −0		test/passthrough_stream_fifo_tb.sv
+18 −1		test/popcount_tb.sv
+1 −1		rtl/cv32e40p_alu.sv
+8 −8		rtl/cv32e40p_cs_registers.sv
+2 −0		rtl/cv32e40p_decoder.sv
+1 −1		rtl/cv32e40p_id_stage.sv
+1 −1		src/systems/pulpopen/dmac_wrap_cl_idma.sv
+1 −1		src/systems/pulpopen/dmac_wrap_fc_idma.sv
+2 −2		rtl/cluster_bus_wrap.sv
+1 −0		rtl/cluster_interconnect_wrap.sv
+49 −0		rtl/udma_i2c_control.sv
+33 −0		rtl/udma_i2c_reg_if.sv
+49 −0		rtl/udma_i2c_top.sv