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Add Apple M1/M2/M3/M4 Linux MIDR detection #385

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Add Apple M1/M2/M3/M4 Linux MIDR detection #385

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13d023f
Add Cortex-A320 to MIDR decode table
fbarchard Apr 28, 2026
5e710ee
Add Apple M1/M2 Linux MIDR detection
fbarchard Apr 28, 2026
8373f61
Add Apple M3/M4 Linux MIDR detection
fbarchard Apr 28, 2026
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2 changes: 2 additions & 0 deletions include/cpuinfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -525,6 +525,8 @@ enum cpuinfo_uarch {
cpuinfo_uarch_cortex_a510 = 0x00300551,
/** ARM Cortex-A520. */
cpuinfo_uarch_cortex_a520 = 0x00300552,
/** ARM Cortex-A320. */
cpuinfo_uarch_cortex_a320 = 0x00300553,
/** ARM Cortex-A710. */
cpuinfo_uarch_cortex_a710 = 0x00300571,
/** ARM Cortex-A715. */
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48 changes: 48 additions & 0 deletions src/arm/uarch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -141,6 +141,9 @@ void cpuinfo_arm_decode_vendor_uarch(
case 0xD87: /* Cortex-A725 */
*uarch = cpuinfo_uarch_cortex_a725;
break;
case 0xD8F: /* Cortex-A320 */
*uarch = cpuinfo_uarch_cortex_a320;
break;
case 0xD8C:
*uarch = cpuinfo_uarch_lumex_c1_ultra;
break;
Expand Down Expand Up @@ -435,6 +438,51 @@ void cpuinfo_arm_decode_vendor_uarch(
midr_get_part(midr));
}
break;
case 'a':
*vendor = cpuinfo_vendor_apple;
switch (midr_get_part(midr)) {
case 0x022:
case 0x024:
case 0x028:
*uarch = cpuinfo_uarch_icestorm;
break;
case 0x023:
case 0x025:
case 0x029:
*uarch = cpuinfo_uarch_firestorm;
break;
case 0x032:
case 0x034:
case 0x038:
*uarch = cpuinfo_uarch_blizzard;
break;
case 0x033:
case 0x035:
case 0x039:
*uarch = cpuinfo_uarch_avalanche;
break;
case 0x042:
case 0x044:
case 0x048:
*uarch = cpuinfo_uarch_coll_sawtooth;
break;
case 0x043:
case 0x045:
case 0x049:
*uarch = cpuinfo_uarch_coll_everest;
break;
case 0x052:
*uarch = cpuinfo_uarch_donan_sawtooth;
break;
case 0x053:
*uarch = cpuinfo_uarch_donan_everest;
break;
default:
cpuinfo_log_warning(
"unknown Apple CPU part 0x%03" PRIx32 " ignored",
midr_get_part(midr));
}
break;
#if CPUINFO_ARCH_ARM
case 'V':
*vendor = cpuinfo_vendor_marvell;
Expand Down
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