A612 supoort on qli2.0 #137
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GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689010/ Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com
Some GPUs like A612 doesn't use a named register range resource. This is because the reg-name property is discouraged when there is just a single resource. To address this, retrieve the 'gmu' register range by its index. It is always guaranteed to be at index 0. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-1-f5a00c5b663f@oss.qualcomm.com
…logic JSON Schema conditionals can become complex and error-prone when combined with regex patterns. To improve readability and maintainability, replace nested if-else blocks with a flattened structure using explicit enums. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-2-f5a00c5b663f@oss.qualcomm.com
A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit) which replaces GMU. But it doesn't do clock or voltage scaling. So we need the gpu core clock in the GPU node along with the power domain to do clock and voltage scaling from the kernel. Update the bindings to describe this GPU. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-3-f5a00c5b663f@oss.qualcomm.com
RGMU a.k.a Reduced Graphics Management Unit is a small state machine with the sole purpose of providing IFPC (Inter Frame Power Collapse) support. Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, it doesn't require iommu. So far, only Adreno 612 GPU has an RGMU core. Document it in qcom,adreno-rgmu.yaml. Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-4-f5a00c5b663f@oss.qualcomm.com
Add the Adreno GPU SMMU node for Talos chipset. Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-5-f5a00c5b663f@oss.qualcomm.com
Add gpu and rgmu nodes for Talos chipset. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-6-f5a00c5b663f@oss.qualcomm.com
Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 105°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-7-f5a00c5b663f@oss.qualcomm.com
Enable GPU for qcs615-ride platform and provide path for zap shader. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-8-f5a00c5b663f@oss.qualcomm.com
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Talos add gpu support for qli2.0
CRs-Fixed: 4389004