Skip to content

Add inline asm support for amdgpu #149793

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Flakebi wants to merge 6 commits into
base: main
Choose a base branch
from
Open

Add inline asm support for amdgpu #149793

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
fc6d00e
Add inline asm support for amdgpu
Flakebi Feb 20, 2026
21d3e57
Split amdgpu inline asm reg classes by size
Flakebi Feb 23, 2026
d959ff1
Add vector types to amdgpu inline asm
Flakebi Feb 23, 2026
dc350d8
Store register size as int instead of listing all
Flakebi Apr 16, 2026
581b55a
Compute amdgpu supported_types dynamically
Flakebi May 11, 2026
4011f0d
Forgot to run tidy
Flakebi May 13, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions compiler/rustc_codegen_gcc/src/asm.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -677,6 +677,8 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
unreachable!("clobber-only")
}
InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "Sg",
InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Vgpr(_)) => "v",
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
Expand Down Expand Up @@ -780,6 +782,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
unreachable!("clobber-only")
}
InlineAsmRegClass::Amdgpu(_) => cx.type_i32(),
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
Expand Down Expand Up @@ -983,6 +986,7 @@ fn modifier_to_gcc(
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
unreachable!("clobber-only")
}
InlineAsmRegClass::Amdgpu(_) => None,
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None,
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,
Expand Down
7 changes: 6 additions & 1 deletion compiler/rustc_codegen_llvm/src/asm.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
match *op {
InlineAsmOperandRef::Out { reg, late, place } => {
let is_target_supported = |reg_class: InlineAsmRegClass| {
for &(_, feature) in reg_class.supported_types(asm_arch, true) {
for &(_, feature) in reg_class.supported_types(asm_arch, true).as_ref() {
if let Some(feature) = feature {
if self
.tcx
Expand Down Expand Up @@ -229,6 +229,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC | InlineAsmArch::Arm => {
constraints.push("~{cc}".to_string());
}
InlineAsmArch::Amdgpu => {}
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
constraints.extend_from_slice(&[
"~{dirflag}".to_string(),
Expand Down Expand Up @@ -698,6 +699,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
| Arm(ArmInlineAsmRegClass::dreg_low8)
| Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
Arm(ArmInlineAsmRegClass::dreg) | Arm(ArmInlineAsmRegClass::qreg) => "w",
Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "s",
Amdgpu(AmdgpuInlineAsmRegClass::Vgpr(_)) => "v",
Hexagon(HexagonInlineAsmRegClass::reg) => "r",
Hexagon(HexagonInlineAsmRegClass::reg_pair) => "r",
Hexagon(HexagonInlineAsmRegClass::preg) => unreachable!("clobber-only"),
Expand Down Expand Up @@ -803,6 +806,7 @@ fn modifier_to_llvm(
modifier
}
}
Amdgpu(_) => None,
Hexagon(_) => None,
LoongArch(_) => None,
Mips(_) => None,
Expand Down Expand Up @@ -883,6 +887,7 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
Arm(ArmInlineAsmRegClass::qreg)
| Arm(ArmInlineAsmRegClass::qreg_low8)
| Arm(ArmInlineAsmRegClass::qreg_low4) => cx.type_vector(cx.type_i64(), 2),
Amdgpu(_) => cx.type_i32(),
Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
Hexagon(HexagonInlineAsmRegClass::reg_pair) => cx.type_i64(),
Hexagon(HexagonInlineAsmRegClass::preg) => unreachable!("clobber-only"),
Expand Down
3 changes: 2 additions & 1 deletion compiler/rustc_hir_typeck/src/inline_asm.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -465,7 +465,8 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
if let InlineAsmRegClass::Err = reg_class {
continue;
}
for &(_, feature) in reg_class.supported_types(asm_arch, allow_experimental_reg)
for &(_, feature) in
reg_class.supported_types(asm_arch, allow_experimental_reg).as_ref()
{
match feature {
Some(feature) => {
Expand Down
21 changes: 21 additions & 0 deletions compiler/rustc_span/src/symbol.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1833,6 +1833,12 @@ symbols! {
self_in_typedefs,
self_struct_ctor,
semiopaque,
sgpr32,
sgpr64,
sgpr96,
sgpr128,
sgpr256,
sgpr512,
sha2,
sha3,
sha512_sm_x86,
Expand Down Expand Up @@ -2237,6 +2243,21 @@ symbols! {
verbatim,
version,
vfp2,
vgpr16,
vgpr32,
vgpr64,
vgpr96,
vgpr128,
vgpr160,
vgpr192,
vgpr224,
vgpr256,
vgpr288,
vgpr320,
vgpr352,
vgpr384,
vgpr512,
vgpr1024,
view_types,
vis,
visible_private_types,
Expand Down
Loading
Loading