Scratch/ronjok/fir scalar 2x2 2x2 pymtl

[rp15]

I am opening this pull request to discuss the necessary modifications to execute scalar FIR PyMTL simulation on 2x2-CGRA grid with 2x2 tiles in every CGRA, moving from a 2x2 CGRA with 4x4 tiles. I have already changed the cfg packets to have

• the correct indexing in CGRA0 (bottom left) (tiles 4, 5 are now tiles 2, 3) and
• move the old CGRA0 tiles 8, 9 to CGRA2 (top left) (CGRA0 tiles 8, 9 are now CGRA 2 tiles 0, 1).
• Also changed expected_complete_sink_out_pkg not to violate the new bit width, but I am not sure what src and dst values should be in this scenario.

Currently getting an error from pytest that simulation exceeds the 200-cycle limit. What else would I need to modify moving forward? Thank you!

[tancheng]

We may need to dump the pymtl simulation traces to see whether operations are correctly executed on each tile.

[rp15]

, recv_from_cpu_pkt.rdy=1, recv_from_cpu_pkt.val=0, send_to_cpu_pkt.msg=IntraCgraPkt: 0->0 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:00|data:00000000.0.0.0|data_addr:00|ctrl:(opt)00|(fu_in)0-0-0-0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0

, send_to_cpu_pkt.rdy=1, send_to_cpu_pkt.val=0,
cycle 199: clk=0, reset=0, recv_from_cpu_pkt.msg=IntraCgraPkt: 2->1 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:00|data:00000000.0.0.0|data_addr:00|ctrl:(opt)00|(fu_in)0-0-0-0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0

, recv_from_cpu_pkt.rdy=1, recv_from_cpu_pkt.val=0, send_to_cpu_pkt.msg=IntraCgraPkt: 0->0 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:00|data:00000000.0.0.0|data_addr:00|ctrl:(opt)00|(fu_in)0-0-0-0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0

, send_to_cpu_pkt.rdy=1, send_to_cpu_pkt.val=0,
cycle 200: clk=0, reset=0, recv_from_cpu_pkt.msg=IntraCgraPkt: 2->1 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:00|data:00000000.0.0.0|data_addr:00|ctrl:(opt)00|(fu_in)0-0-0-0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0

, recv_from_cpu_pkt.rdy=1, recv_from_cpu_pkt.val=0, send_to_cpu_pkt.msg=IntraCgraPkt: 0->0 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:00|data:00000000.0.0.0|data_addr:00|ctrl:(opt)00|(fu_in)0-0-0-0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0

, send_to_cpu_pkt.rdy=1, send_to_cpu_pkt.val=0,
FAILED

I get these messages printed to the terminal during the run; I haven't fully understood how to interpret it. Is this a good starting point or do you think we need different info?

[tancheng]

right, that's the dump trace in every module. or you can use python print() in the FU you want to check, e.g.,

VectorCGRA/fu/single/MulRTL.py

Line 65 in 4d4937a

s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload

to see what is the value during simulation.