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90nm

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priyanshu-saurabh / digitally-enhanced-multibit-sigma-delta-adc

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Digitally-enhanced second-order multi-bit Sigma-Delta ADC designed in 90 nm CMOS, featuring DWA-based DAC linearization, drift-compensated switched-capacitor integrators, and reconfigurable OSR modes. Implemented and verified in Cadence Virtuoso with full PVT, mismatch, loop-stability, and post-layout (PEX) analysis.

adc cadence-virtuoso self-calibration dwa 90nm multi-bit-modulation
  • Updated May 15, 2026

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