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asynchronous-fifo
Here are 9 public repositories matching this topic...
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog
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May 10, 2019 - Verilog
An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
This repository contains an asynchronous FIFO design and a comprehensive UVM testbench for its functional verification. It demonstrates a robust, real-world approach to digital design and verification.
asynchronous-fifo uvm-verification asynchronous-fifo-design-verification asynchronous-fifo-uvm-based-design-verification
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Sep 22, 2025 - SystemVerilog
Parameterized Asynchronous FIFO in Verilog using Gray Code pointers with Full, Empty, Almost Full, and Almost Empty flags for safe clock domain crossing (CDC).
asynchronous verilog vivado fifo cdc asynchronous-fifo almost-full almost-empty full-empty fifo-asynchronous
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May 8, 2026 - Verilog
A highly parameterized, synthesizable Asynchronous FIFO designed to safely transfer data between two independent, asynchronous clock domains. This project demonstrates core VLSI concepts including metastability prevention, Gray code synchronization, and static timing closure on an FPGA architecture.
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May 24, 2026 - Verilog
Asynchronous FIFO with CDC Reliability Analyzer built from scratch in Verilog. Gray-code pointers, 2-FF synchronizers, randomized stress testbench, timing closure on Artix-7 (WNS = +6.31 ns). No IP cores used.
fpga verilog hardware-designs cdc vlsi digital-design xilinx-vivado metastability clock-domain-crossing artix-7 asynchronous-fifo rtl-design
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Apr 24, 2026 - Verilog
Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog
asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design
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Nov 20, 2025 - SystemVerilog
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