An AXI4 crossbar implementation in SystemVerilog

RISCV CPU implementation in SystemVerilog

A Python tool for computing and plotting currents and voltages in passive crossbar arrays.

Lightweight Module for Asynchronous Event Driven Systems

A general framework for microservice based distributed applications

HDL components to build a customized Wishbone crossbar switch

UAV simulator that sends NMEA sentences to external devices

The XBR Protocol - blockchain protocol for decentralized open data markets (https://pypi.org/project/xbr/)

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

Firmware for the Mockingbird Telephone Exchange master controller

Uses WAMP meta events and meta procedures to collect and expose metrics.

DUB Sparsity for Crossbars

[Nature Communications 2025] "Random resistive memory-based extreme point learning machine for unified visual processing."

An iterator-based implementation of the locality-preserving one-sided binary tree - crossbar switch wiring design algorithm

A metadata flow manager

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

Crossbar Parasitics Simulator – A tool for benchmarking parasitic resistance models in RRAM crossbars and evaluating neural networks under realistic hardware constraints.

A free platform for managing sports teams, leagues, and clubs. Simplify your season with tools for rostering, scheduling, and communication.

A framework for offloading parts of an Android mobile application to nearby Android mobile devices using Wifi-Direct , edge devices (cloudlets), and remote clouds

This is a 3D Maze game based on https://github.com/wwwtyro/Astray. This version is not controlled by keyboards instead using smartphone gyroscope. The gyroscope data is exposed via chrome browser which is transferred via WAMP protocol to the Crossbar.io router.