vlsi-verification

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Gagandeep-25 / SV_and_UVM_mini_project

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System verilog and UVM mini projects

coverage randomization verilog systemverilog uvm digitaldesign functionalverification vlsi-verification

Updated Dec 24, 2025
SystemVerilog

Mummanajagadeesh / 4-bit-ripple-carry-adder

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VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation

testing simulation verilog hdl vlsi icarus atpg fault-modeling vlsi-testing stuck-at-faults vlsi-verification

Updated Sep 23, 2025
Python

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vlsi-verification

Here are 2 public repositories matching this topic...

Gagandeep-25 / SV_and_UVM_mini_project

Mummanajagadeesh / 4-bit-ripple-carry-adder

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Add this topic to your repo