VLSI lab - PoliTO
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Mage-and-Rogue
Mage-and-Rogue PublicTemplate-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
Python 7
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Repositories
- cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
vlsi-lab/cva6’s past year of commit activity - Mage-and-Rogue Public
Template-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
vlsi-lab/Mage-and-Rogue’s past year of commit activity - CHIMERA Public
vlsi-lab/CHIMERA’s past year of commit activity - len5 Public
LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
vlsi-lab/len5’s past year of commit activity - png2gds Public
Convert a PNG image into a GDSII cell made of a grid of rectangles on a single layer.
vlsi-lab/png2gds’s past year of commit activity - area-plot-post-syn Public
vlsi-lab/area-plot-post-syn’s past year of commit activity
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