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[26.04_linux-nvidia-bos] PCI: mirror PI7C9X3G606GPC Port 4 BAR0#443

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[26.04_linux-nvidia-bos] PCI: mirror PI7C9X3G606GPC Port 4 BAR0#443
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@nirmoy nirmoy commented May 27, 2026

Summary

  • Backport the PI7C9X3G606GPC Port 4 BAR0 workaround from the 6.17 PR.
  • Add a PCI final/resume quirk to mirror the upstream BAR0 value into downstream Port 4 BAR0.
  • Scope the WAR to the Diodes-confirmed OS-visible Tile0/P4 mapping: upstream bus + 1, device 04, function 0.
  • Port 4 BAR0 may read back as zero through normal PCI config space even after a successful write, so the quirk rewrites BAR0 whenever it runs.

Validation

  • Same source-level patch as the 6.17 PR; cherry-pick applied cleanly to 26.04_linux-nvidia-bos.
  • Expected dmesg when the WAR runs:
pci 0002:a2:04.0: wrote upstream BAR 0 0x10c00000 to Port 4 BAR 0 for PI7C9X3G606GPC workaround
  • The BAR value is platform/boot dependent. In the 6.17 Quark test run, Linux reassigned upstream BAR0 for 0002:a1:00.0 from 0x10300000 to 0x10c00000, then the quirk wrote 0x10c00000 to 0002:a2:04.0 Port 4 BAR0.
  • Normal config-space readback of Port 4 BAR0 still returns 0 on this device, so setpci readback is not a valid failure signal for the WAR.
  • A Diodes-provided BMC/I2C debug readback sequence returned non-zero Port 4 BAR0 bytes, 0x10 0xc0 0x00 0x00, matching 0x10c00000. That sequence uses special CPED/CDEP programming and is not a supported production validation path on this platform, so further validation should avoid it.

Fresh BOS package/boot validation is still pending.

References

Launchpad: https://bugs.launchpad.net/ubuntu/+source/linux-nvidia-6.17/+bug/2154457

6.17 PR: #442
NVBug: https://nvbugspro.nvidia.com/bug/6205517
NVBug: https://nvbugspro.nvidia.com/bug/6134331

@nirmoy nirmoy added the help wanted Extra attention is needed label May 27, 2026
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github-actions Bot commented May 27, 2026

PR Validation Report

Patchscan ✅ No Missing Fixes

All cherry-picked commits checked — no missing upstream fixes found.

PR Lint ❌ Errors found

Details
Checking 1 commits...

Cherry-pick digest:
E: 5f3ea0445555 ("NVIDIA: SAUCE: PCI: quirks: mirror PI7C9"): patch-ID mismatch with upstream 5edb468a3760
E: 5f3ea0445555 ("NVIDIA: SAUCE: PCI: quirks: mirror PI7C9"): SoB chain problem: MISSING: no Signed-off-by after (cherry picked from commit ...)
┌──────────────┬──────────────────────────────────────────────────────────────────┬────────────┬─────────┬───────────────────────────┐
│ Local        │ Referenced upstream / Patch subject                              │ Patch-ID   │ Subject │ SoB chain                 │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ 5f3ea0445555 │ 5edb468a3760 NVIDIA: SAUCE: PCI: quirks: mirror PI7C9X3G606GPC P │ MISMATCH   │ match   │ MISSING: no Signed-off-by │
└──────────────┴──────────────────────────────────────────────────────────────────┴────────────┴─────────┴───────────────────────────┘

Lint: all checks passed.

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nirmoy commented May 27, 2026

Boro review

Latest watcher review: open review

Head: 5f3ea0445555

This comment is maintained by nv-pr-bot. It is updated when the GitHub watcher publishes a newer review.

Some Pericom/Diodes PI7C9X3G606GPC switches require downstream Port 4
BAR0 to mirror the upstream port BAR0. Firmware may apply this during
boot, but Linux PCI resource assignment can move the upstream BAR0 and
leave Port 4 without the required mirror.

Add a final and resume quirk for downstream Port 4. The quirk verifies
that the immediate upstream bridge is the same switch, then writes Port 4
BAR0 from the upstream BAR0 after resource assignment and after resume.
Port 4 BAR0 may read back as zero even after a successful write, so the
write must be validated by platform-specific means.

Change-Id: I139ffad14467cabd4cc8491823f36e34bc876ea1
Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>
(cherry picked from commit 5edb468)
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