feat(c-prime-isa): LOAD-PHYS-CONST opcode 0xDE spec · L-DPC24 Lane C'#632
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feat(c-prime-isa): LOAD-PHYS-CONST opcode 0xDE spec · L-DPC24 Lane C'#632gHashTag wants to merge 1 commit into
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Opcode: 0xDE (TRI-27 ISA sacred range 0xD0..0xE0) Mnemonic: LDPC Encoding: [0xDE:8b][rd:5b][imm7:7b][reserved:12b] = 32-bit Semantics: R[rd] <- SacredROM[imm7] 75-cell Sacred ROM, cells 0-3: phi, gamma=phi^-3, C=phi^-1, G=pi^3*gamma^2/phi R18 LAYER-FROZEN: ROM constants are placeholders pending Lane E P3 frozen-hash. Anchor: phi^2 + phi^-2 = 3 Closes: gHashTag/trinity-fpga#99
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This was referenced May 15, 2026
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LOAD-PHYS-CONST (LDPC) — Opcode 0xDE · L-DPC24 Lane C'
Closes: gHashTag/trinity-fpga#99
What this PR does
Adds the ISA specification for the
LDPC(LOAD-PHYS-CONST) instruction, opcode0xDE, in the TRI-27 ISA sacred range0xD0..0xE0.Per the Quantum Brain 1:1 Silicon principle, physics constants (φ, γ=φ⁻³, C=φ⁻¹, G=π³γ²/φ) are baked into silicon and accessed via the 75-cell Sacred ROM — not loaded from mutable memory.
File added
specs/isa/LOAD_PHYS_CONST_0xDE.mdSpec highlights
0xDE0xD0..0xE0LDPC rd, imm7[0xDE:8b][rd:5b][imm7:7b][reserved:12b](32-bit)R[rd] ← SacredROM[imm7]imm7 ∈ [0..74];[75..127]= UBSacred ROM index 0–3 (placeholder, R18 LAYER-FROZEN)
Paired RTL hook PR
The paired hardware implementation PR is on
gHashTag/tt-trinity-holo:feat(c-prime-rtl): LOAD-PHYS-CONST 0xDE hardware hook · L-DPC24 Lane C'Anchor
φ²+φ⁻²=3