[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)#10025
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[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)#10025
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Fixes #9972 |
…m#9972) - Emit generate/case scope names before instance segments, matching `GenerateOp` / `GenerateCaseOp` emission (including `legalizeName` order for case labels)
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uenoku
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Mar 24, 2026
uenoku
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uenoku
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Thank you for working on this!
…#10025) - Follow the reviewer's suggestions
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@uenoku Thanks for the review! I’ve addressed the comments and pushed updates. Could you please take another look when you have a chance? Thanks!! |
uenoku
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Mar 25, 2026
fix nit: please avoid unnecessary allocation of strings Co-authored-by: Hideto Ueno <uenoku.tokotoko@gmail.com>
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The CI seems to be failing, but 'Conversion/ExportVerilog/sv-dialect.mlir' tests pass on my local machine. @uenoku Would you be able to help take a look when you have a moment? Thanks in advance! |
uenoku
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Apr 3, 2026
| let arguments = (ins TypedAttrInterface:$cond, | ||
| PatternArrayAttr:$casePatterns, StrArrayAttr:$caseNames); | ||
| PatternArrayAttr:$casePatterns, StrArrayAttr:$caseNames, | ||
| OptionalAttr<StrArrayAttr>:$verilogCaseNames); |
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I know it's a bit weird but could you not make verilogCaseNames as part of ODS defined attributes because we don't want to expose verilog names here as API?
uenoku
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Apr 3, 2026
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| module.walk([&](GenerateCaseOp genCase) { | ||
| llvm::StringMap<size_t> nextGenIds; | ||
| SmallVector<Attribute> legalizedNames; | ||
| for (Attribute name : genCase.getCaseNames()) { | ||
| StringRef legal = | ||
| sv::legalizeName(cast<StringAttr>(name).getValue(), nextGenIds, | ||
| options.caseInsensitiveKeywords); | ||
| legalizedNames.emplace_back(StringAttr::get(ctxt, legal)); | ||
| } | ||
| genCase.setVerilogCaseNamesAttr(ArrayAttr::get(ctxt, legalizedNames)); | ||
| }); |
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nit: Could you do this in a walk above?
uenoku
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Apr 3, 2026
| options.caseInsensitiveKeywords); | ||
| legalizedNames.emplace_back(StringAttr::get(ctxt, legal)); | ||
| } | ||
| genCase.setVerilogCaseNamesAttr(ArrayAttr::get(ctxt, legalizedNames)); |
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As I mentioned above could you use discardable attribute hw.verilogCaseNames ?
uenoku
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Apr 3, 2026
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| segments.push_back(SmallString<32>(legal)); | ||
| break; | ||
| } | ||
| } else if (auto gen = dyn_cast<GenerateOp>(parentOp)) { | ||
| StringRef name = ExportVerilog::getSymOpName(gen); | ||
| segments.push_back(SmallString<32>(name)); |
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I think this causes UAF.
Suggested change
| segments.push_back(SmallString<32>(legal)); | |
| break; | |
| } | |
| } else if (auto gen = dyn_cast<GenerateOp>(parentOp)) { | |
| StringRef name = ExportVerilog::getSymOpName(gen); | |
| segments.push_back(SmallString<32>(name)); | |
| segments.push_back(legal); | |
| break; | |
| } | |
| } else if (auto gen = dyn_cast<GenerateOp>(parentOp)) { | |
| StringRef name = ExportVerilog::getSymOpName(gen); | |
| segments.push_back(name); |
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GenerateOp/GenerateCaseOpemission (includinglegalizeNameorder for case labels)