[hw] CVA6 updated with HPDCache#520
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This moves the Mocha specific changes to the top instead of a commit in the vendored in repository.
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This commit also switches CVA6's core file to use the HPDCache configuration and to depend on the HPDCache. It also adds the License information for the HPDCache in REUSE.toml
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If we intend to merge the testrig harness into mocha, its worth noting that the rvfi_dii_generator module within this generate block is currently used by the harness for instruction injection. In this case since the ports are just a subset of the icache ports, I think it should be possible to hook the injector into the icache fairly easily.
The only challenge in this case is omitting the real icache during elaboration, and taking the DII instruction injector instead, which could be solved via a systemverilog config file (if we dont want to change the .core files). This would add a little bit of complexity, but could still work cleanly.
Alternatively, we could leave the generator instantiation in.
Both approaches are OK from my perspective, just a matter of taste and weather we are OK with having simulation-only modules instantiated explicitly inside the RTL.
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I think for now we can leave it in but I agree that in the long run we should not have simulation only modules corrupting our RTL.
Update code from upstream repository https://github.com/Capabilities-Limited/cv-hpdcache.git to revision 07f4ebe7bd074e2f82f6b10c2386026bc12455d8 Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
This is a big code change because there has been a rebase on upstream non-CHERI CVA6 as well as work to enable HPDCache. This vendor is based on the following release: https://github.com/Capabilities-Limited/cheri-cva6/releases/tag/cva6-april-2026
PCC specific types have been removed in favour of register types, make the appropriate change when definding the boot capability.
Using $clog2 to determine the width of a signal that has size 1 will erroneously give zero. This changes that.
Ibex is not integrated in Mocha, so this can be removed.
Usage is zero when FIFO is empty as well as full, so we need to take into account the full signal when assigning to empty.
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I'm marking this as draft because there are X propagation issues in CHERI mode. |
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This is the first major update of CVA6 since our initial integration. The core has seen quite a few fixes and most importantly the HPDCache is now integrated for use.
Closes: #245