[hw] CVA6 updated with HPDCache

hw/ip/common_cells/rtl/fifo_v3.sv

@@ -54,7 +54,7 @@ module fifo_v3 #(
   );
 
   assign full_o  = full | err | ~wready;
-  assign empty_o = (usage == '0) | err;
+  assign empty_o = ((usage == '0) & ~full) | err;
   assign usage_o = usage;
 
   assign unused_testmode = testmode_i;

hw/top_chip/lint/top_chip_system.vlt

@@ -7,7 +7,7 @@
 `verilator_config
 
 // Initialising all RVFI signals to zero is OK in this case.
-lint_off -rule WIDTHCONCAT -file "*/cva6_cheri/core/cva6_rvfi_probes.sv" -match "*More than a 8k bit replication is probably wrong: 8461"
+lint_off -rule WIDTHCONCAT -file "*/cva6_cheri/core/cva6_rvfi_probes.sv" -match "*More than a 8k bit replication is probably wrong: 8475"
 
 // This is only when data width is equal to one.
 lint_off -rule UNSIGNED -file "*/rtl/rr_arb_tree.sv" -match "*Comparison is constant due to unsigned arithmetic"
@@ -295,3 +295,17 @@ lint_off -rule UNUSEDSIGNAL -file "*/lowrisc_ip_rom_ctrl*/rtl/rom_ctrl.sv" -matc
 lint_off -rule UNUSEDSIGNAL -file "*/lowrisc_ip_rom_ctrl*/rtl/rom_ctrl.sv" -match "*kmac_rom_vld_outer*"
 lint_off -rule UNUSEDSIGNAL -file "*/lowrisc_ip_rom_ctrl*/rtl/rom_ctrl.sv" -match "*kmac_rom_last_outer*"
 lint_off -rule UNUSEDSIGNAL -file "*/lowrisc_ip_rom_ctrl*/rtl/rom_ctrl.sv" -match "*kmac_err*"
+
+// HPDCache
+lint_off -rule CASEINCOMPLETE -file "*/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv" -match "*req_i*" // Default values specified outside case
+lint_off -rule UNDRIVEN -file "*/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv" -match "*hpdcache_req_o*"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/common/hpdcache_fxarb.sv"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/hpdcache.sv"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/hpdcache_core_arbiter.sv"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/hpdcache_ctrl.sv"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/hpdcache_ctrl_pe.sv"
+lint_off -rule UNOPTFLAT -file "*/hpdcache/rtl/src/hpdcache_miss_handler.sv"
+lint_off -rule UNUSEDPARAM -file "*/hpdcache/rtl/*/*.sv" // Harmless warning for vendored in code.
+lint_off -rule UNUSEDSIGNAL -file "*/hpdcache/rtl/*/*.sv" // Harmless warning for vendored in code.
+lint_off -rule WIDTHEXPAND -file "*/hpdcache/rtl/*/*.sv" // Not worth fixing width errors in vendored code.
+lint_off -rule WIDTHTRUNC -file "*/hpdcache/rtl/*/*.sv" // Not worth fixing width errors in vendored code.

hw/top_chip/rtl/top_chip_system.sv

@@ -76,8 +76,12 @@ module top_chip_system #(
   // CVA6 configuration
   function automatic config_pkg::cva6_cfg_t build_cva6_config(config_pkg::cva6_user_cfg_t CVA6UserCfg);
     config_pkg::cva6_user_cfg_t cfg = CVA6UserCfg;
+    // Extensions
     cfg.RVZiCond                    = bit'(0);
+    cfg.RVF                         = bit'(0);
+    cfg.RVD                         = bit'(0);
     cfg.CvxifEn                     = bit'(0);
+    // Memory map
     cfg.DmBaseAddress               = top_pkg::DebugMemBase;
     cfg.NrExecuteRegionRules        = unsigned'(4);
     cfg.ExecuteRegionAddrBase       = 1024'({top_pkg::DRAMBase,
@@ -95,9 +99,9 @@ module top_chip_system #(
   endfunction
 
   localparam config_pkg::cva6_cfg_t CVA6Cfg = build_cva6_config(cva6_config_pkg::cva6_cfg);
-  cva6_cheri_pkg::cap_pcc_t boot_cap;
+  cva6_cheri_pkg::cap_reg_t boot_cap;
   always_comb begin : gen_boot_cap
-    boot_cap                = cva6_cheri_pkg::PCC_ROOT_CAP;
+    boot_cap                = cva6_cheri_pkg::REG_ROOT_CAP;
     boot_cap.addr           = top_pkg::RomCtrlMemBase + 'h80;
     boot_cap.flags.int_mode = 1'b1;
   end

hw/vendor/REUSE.toml

@@ -3,7 +3,7 @@
 version = 1
 
 [[annotations]]
-path = ["lowrisc_ibex/**", "lowrisc_ip/**"]
+path = ["lowrisc_ip/**"]
 SPDX-FileCopyrightText = "lowRISC Contributors."
 SPDX-License-Identifier = "Apache-2.0"
 
@@ -41,6 +41,14 @@ SPDX-FileCopyrightText = [
     "2025 Capabilities Limited."
 ]
 
+[[annotations]]
+path = ["hpdcache/**"]
+SPDX-License-Identifier = "Apache-2.0 WITH SHL-2.1"
+SPDX-FileCopyrightText = [
+    "Copyright 2023,2024 Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA)",
+    "Copyright 2025 Univ. Grenoble Alpes, Inria, TIMA Laboratory"
+]
+
 [[annotations]]
 path = ["axi_riscv_atomics/**"]
 SPDX-License-Identifier = "SHL-0.51"

hw/vendor/cva6.core

@@ -11,14 +11,15 @@ filesets:
     depend:
       - pulp-platform.org::axi
       - lowrisc:common_cells:all
+      - lowrisc:cosmic:hpdcache
       - lowrisc:prim:lfsr
     files:
       # Includes.
       - cva6_cheri/core/include/rvfi_types.svh: {is_include_file: true, include_path: cva6_cheri/core/include}
       - cva6_cheri/core/include/cvxif_types.svh: {is_include_file: true, include_path: cva6_cheri/core/include}
       # Packages.
       - cva6_cheri/core/include/config_pkg.sv
-      - cva6_cheri/core/include/cv64a6_imafdchzcheri_sv39_config_pkg.sv
+      - cva6_cheri/core/include/cv64a6_imafdczcheri_sv39_hpdcache_wb_config_pkg.sv
       - cva6_cheri/core/include/riscv_pkg.sv
       - cva6_cheri/core/include/cva6_cheri_pkg.sv
       - cva6_cheri/core/include/wt_cache_pkg.sv
@@ -30,6 +31,7 @@ filesets:
       - cva6_cheri/core/cva6.sv
       - cva6_cheri/core/cva6_rvfi_probes.sv
       - cva6_cheri/core/alu.sv
+      - cva6_cheri/core/alu_wrapper.sv
       - cva6_cheri/core/branch_unit.sv
       - cva6_cheri/core/compressed_decoder.sv
       - cva6_cheri/core/macro_decoder.sv
@@ -70,18 +72,6 @@ filesets:
       - cva6_cheri/core/frontend/instr_scan.sv
       - cva6_cheri/core/frontend/instr_queue.sv
       - cva6_cheri/core/frontend/frontend.sv
-      # Cache.
-      - cva6_cheri/core/cache_subsystem/wt_dcache_ctrl.sv
-      - cva6_cheri/core/cache_subsystem/wt_dcache_mem.sv
-      - cva6_cheri/core/cache_subsystem/wt_dcache_missunit.sv
-      - cva6_cheri/core/cache_subsystem/wt_dcache_wbuffer.sv
-      - cva6_cheri/core/cache_subsystem/wt_dcache.sv
-      - cva6_cheri/core/cache_subsystem/cva6_icache.sv
-      - cva6_cheri/core/cache_subsystem/wt_cache_subsystem.sv
-      - cva6_cheri/core/cache_subsystem/wt_axi_adapter.sv
-      - cva6_cheri/common/local/util/tc_sram_wrapper.sv
-      - cva6_cheri/common/local/util/sram.sv
-      - cva6_cheri/common/local/util/sram_cache.sv
       # Physical memory protection.
       - cva6_cheri/core/pmp/src/pmp.sv
       - cva6_cheri/core/pmp/src/pmp_entry.sv
@@ -91,6 +81,15 @@ filesets:
       - cva6_cheri/core/cva6_mmu/cva6_ptw.sv
       - cva6_cheri/core/cva6_mmu/cva6_tlb.sv
       - cva6_cheri/core/cva6_mmu/cva6_shared_tlb.sv
+      # HPDCache
+      - cva6_cheri/common/local/util/sram.sv
+      - cva6_cheri/common/local/util/sram_cache.sv
+      - cva6_cheri/common/local/util/tc_sram_wrapper.sv
+      - cva6_cheri/core/cache_subsystem/cva6_hpdcache_subsystem.sv
+      - cva6_cheri/core/cache_subsystem/cva6_icache.sv
+      - cva6_cheri/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
+      - cva6_cheri/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
+      - cva6_cheri/core/cache_subsystem/cva6_hpdcache_wrapper.sv
     file_type: systemVerilogSource
 
   files_model:

hw/vendor/cva6_cheri.lock.hjson

@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/cva6-cheri.git
-    rev: 94a9d6f4eb2f7d59d9e66db7c39b522224312768
+    rev: 3c596eb647692e34df246401945804b5a5931041
   }
 }

hw/vendor/cva6_cheri/.gitlab-ci.yml

@@ -238,19 +238,20 @@ hello-pk:
     - when: manual
       allow_failure: true
 
-iti-test:
+it-test:
   extends:
     - .synthesis_test
   variables:
-    DASHBOARD_JOB_TITLE: "ITI test"
-    DASHBOARD_JOB_DESCRIPTION: "Short test to challenge the Instruction Trace Interface"
+    DASHBOARD_JOB_TITLE: "Instruction Trace test"
+    DASHBOARD_JOB_DESCRIPTION: "Test to Challenge the Hardware flow of the Instruction Tracer"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Basic"
     DV_SIMULATORS: "vcs-testharness"
   script:
-    - bash verif/regress/iti_test.sh
-    - diff .gitlab-ci/iti_reference.trace .gitlab-ci/iti.trace
+    - python3 .gitlab-ci/scripts/report_fail.py
+    - bash verif/regress/Instr_tracing_test.sh ../tests/custom/ITI/test_iti_asm.o
     - python3 .gitlab-ci/scripts/report_pass.py
+    - cp -r verif/sim/Instr_tracing_artifact artifacts/
 
 spyglass:
   extends:

hw/vendor/cva6_cheri/.gitmodules

@@ -21,7 +21,7 @@
 	url = https://github.com/lowRISC/ariane-ethernet.git
 [submodule "corev_apu/src/axi_riscv_atomics"]
 	path = corev_apu/src/axi_riscv_atomics
-	url = https://github.com/pulp-platform/axi_riscv_atomics.git
+	url = https://github.com/ninolomata/axi_riscv_atomics.git
 [submodule "corev_apu/riscv-dbg"]
 	path = corev_apu/riscv-dbg
 	url = https://github.com/pulp-platform/riscv-dbg.git
@@ -42,7 +42,7 @@
 	url = https://github.com/openhwgroup/cvfpu.git
 [submodule "core/cache_subsystem/hpdcache"]
 	path = core/cache_subsystem/hpdcache
-	url = https://github.com/openhwgroup/cv-hpdcache.git
+	url = https://github.com/Capabilities-Limited/cv-hpdcache.git
 [submodule "verif/sim/dv"]
 	path = verif/sim/dv
 	url = https://github.com/google/riscv-dv.git
@@ -57,7 +57,7 @@
 	url = https://github.com/pulp-platform/gpio.git
 [submodule "vendor/zero-day/axi_tagcontroller"]
 	path = vendor/zero-day/axi_tagcontroller
-	url = https://github.com/ninolomata/axi_cheri_tagcontroller.git
+	url = https://github.com/Capabilities-Limited/axi_cheri_tagcontroller.git
 [submodule "corev_apu/tb/tb_testRig_cheri/src/RVFI-DII-utils"]
 	path = corev_apu/tb/tb_testRig_cheri/src/RVFI-DII-utils
 	url = https://github.com/CTSRD-CHERI/RVFI-DII-utils.git

hw/vendor/cva6_cheri/Bender.yml

@@ -10,12 +10,13 @@ dependencies:
   axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 }
   common_cells:
     { git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 }
-  fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", version: 0.7.0 }
+  fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", rev: 58ca3c3 } # branch: develop
   tech_cells_generic:
     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
 
 export_include_dirs:
   - core/include
+  - core/cache_subsystem/hpdcache/rtl/include
 
 sources:
   - include_dirs:
@@ -35,6 +36,14 @@ sources:
         files:
           - core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
 
+      - target: cv64a6_imafdc_sv39_hpdcache
+        files:
+          - core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+
+      - target: cv64a6_imafdc_sv39_hpdcache_wb
+        files:
+          - core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv
+
       - target: cv64a6_imafdch_sv39
         files:
           - core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -55,6 +64,14 @@ sources:
         files:
           - core/include/cv32a6_imafc_sv32_config_pkg.sv
 
+      - target: cv32a60x
+        files:
+          - core/include/cv32a60x_config_pkg.sv
+
+      - target: cv32a65x
+        files:
+          - core/include/cv32a65x_config_pkg.sv
+
       # General config infrastructure
       - core/include/riscv_pkg.sv
       - core/include/ariane_pkg.sv
@@ -65,7 +82,7 @@ sources:
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       # MMU
-      - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32)
+      - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32)
         files:
           - core/cva6_mmu/cva6_tlb.sv
           - core/cva6_mmu/cva6_shared_tlb.sv
@@ -75,6 +92,7 @@ sources:
       # Packages
       - core/include/wt_cache_pkg.sv
       - core/include/std_cache_pkg.sv
+      - core/include/aes_pkg.sv
 
       # Extension Interface
       - core/cvxif_example/include/cvxif_instr_pkg.sv
@@ -89,7 +107,9 @@ sources:
       - core/cva6_fifo_v3.sv
       # Top-level source files (not necessarily instantiated at the top of the cva6).
       - core/cva6.sv
+      - core/aes.sv
       - core/alu.sv
+      - core/alu_wrapper.sv
       - core/fpu_wrap.sv # depends on fpnew_pkg, above
       - core/branch_unit.sv
       - core/compressed_decoder.sv
@@ -144,6 +164,61 @@ sources:
       - core/cache_subsystem/cache_ctrl.sv
       - core/cache_subsystem/std_nbdcache.sv
       - core/cache_subsystem/std_cache_subsystem.sv
+      # HPDCache sources
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv
+      - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv
+      - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv
+      - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv
+      - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv
+      - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv
+      - core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv
+      # HPDCache integration
+      - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
+      - core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
+      - core/cache_subsystem/cva6_hpdcache_subsystem.sv
+      - core/cache_subsystem/cva6_hpdcache_wrapper.sv
+      # HPDCache SRAM models
+      - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv
+      - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv
 
       # Physical Memory Protection
       - core/pmp/src/pmp.sv
@@ -161,6 +236,7 @@ sources:
         files:
           - common/local/util/tc_sram_wrapper.sv
           - common/local/util/sram_cache.sv
+          - common/local/util/tc_sram_wrapper_cache_techno.sv
 
       - target: all(fpga, xilinx)
         include_dirs:

hw/vendor/cva6_cheri/Flist.ariane

@@ -60,6 +60,7 @@ vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
 vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv
 core/cache_subsystem/axi_adapter.sv
 core/alu.sv
+core/alu_wrapper.sv
 core/fpu_wrap.sv
 corev_apu/src/ariane.sv
 core/cva6.sv