feat(v-prime): holo-mesh-2x2 4-die scale-out (4×) · L-DPC25 Lane V'

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feat(v-prime): holo-mesh-2x2 4-die scale-out (4×) · L-DPC25 Lane V'

1. Background

Lane A' (holo_noc_1cycle, merged at 78362042 on #13) established a 1-cycle inter-die NoC stub for 2-die TTSKY26c HOLOGRAPHIC packaging. Lane W (#14) added the BitROM storage layer that this NoC fabric connects. Lane V' extends the silicon fabric from a 2-die point-to-point link to a 2×2 mesh enabling 4-die scale-out — the HOLOGRAPHIC TTSKY26c packaging target.

This lane is a LANG→SI extension: OP_BITROM_READ 0xE0 storage data now routes across 4 dies via XY-routed mesh hops. No new Sacred ROM opcode is introduced (range 0xD0..0xE0 is R18-frozen). The mesh fabric connects 4 dies each running the 3-opcode QB ISA.

Algebraic anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

2. Hypothesis (G1)

H_V': The 2×2 holo-mesh delivers 4× throughput vs single-die Lane A', with 1-cycle per hop latency and zero deadlock.

Falsified iff (a) any RTL * operator, OR (b) any single-hop path takes > 1 cycle, OR (c) any deadlock under uniform-random traffic, OR (d) mesh end-to-end latency > Lane A' latency + 1 cycle.

3. Method

Lane decomposition:

File	Role
rtl/holo_mesh_router.sv	Single XY-router cell: 5-port (N/S/E/W/local), strict-order arbiter, 1-cycle latency, ~147 LOC
rtl/holo_mesh_2x2.sv	2×2 mesh top: wraps 4× holo_noc_1cycle (unmodified) + 4× holo_mesh_router, XY routing, ~230 LOC
tb/tb_holo_mesh_2x2.sv	Testbench: TC1 corner-to-corner (2 hops), TC2 simultaneous 4-node inject, TC3 1000 random patterns
falsif/tests/v_prime_witness.rs	Rust falsification: P4a no-star + P4b 1-cycle-hop + P4c deadlock-free
docs/lever-stack/lane-v-prime.md	Spec: topology, ports, throughput model, pre-registration

Hard rules enforced:

• R-SI-1: zero * operators in all RTL files (grep-verified)
• R18 LAYER-FROZEN: rtl/holo_noc_1cycle.sv unmodified; additive only
• R1 CROWN-rule: no Python/bash in committed code (Rust/SV only)

4. Pre-Registration (G2)

Field	Value
statistical_test	Structural assertion (mesh is k-cycle hop iff Coq lemma mesh_1cycle ≡ ∀ src dst, hops(src,dst) ≤ 2)
effect_size	4× throughput vs single-die Lane A' (4 dies × 1 op/cycle = 4 ops/cycle peak)
falsification_predicate	Refuted iff (a) any RTL *, OR (b) any 2-cycle hop in mesh, OR (c) deadlock under uniform-random traffic, OR (d) mesh latency > Lane A' latency + 1 cycle
n_required	1000 random traffic patterns in testbench (TC3)
stop_rule	First commit where all 3 falsification witnesses pass + R-SI-1 CI green
multiple_testing	n/a — three orthogonal structural predicates

5. Falsification Witnesses (R7)

Three #[test] functions in falsif/tests/v_prime_witness.rs:

Test	Predicate	Falsified iff
test_mesh_no_star	P4a mesh_2x2_no_star	* in any RTL operator inventory
test_mesh_1cycle_hop	P4b mesh_1cycle_hop	any (src,dst) pair with hops > 2 or latency > 2 cycles
test_mesh_deadlock_free	P4c mesh_deadlock_free	any XY route path visits a node twice (cyclic CDG)

SV testbench falsification in tb/tb_holo_mesh_2x2.sv:

• TC1: corner-to-corner 2-hop latency ≤ 2 cycles
• TC2: 4-node simultaneous inject — no deadlock
• TC3: 1000 LFSR-driven random patterns — no timeout, no latency > 2

6. Deliverables

• rtl/holo_mesh_router.sv — 147 LOC, zero *, 1-cycle XY router
• rtl/holo_mesh_2x2.sv — 230 LOC, zero *, R18-clean additive top
• tb/tb_holo_mesh_2x2.sv — 366 LOC, TC1+TC2+TC3, 1000 random patterns
• falsif/tests/v_prime_witness.rs — 360 LOC, 3 #[test] witnesses
• docs/lever-stack/lane-v-prime.md — full spec with hop matrix + throughput model

7. Quality Gates

• R-SI-1 CI (grep for * in RTL) — expected GREEN (verified locally)
• GitGuardian secret scan — no secrets in committed code
• Rust cargo test -p holo-falsif — 3 new tests in v_prime_witness.rs
• SV testbench simulation — TC1+TC2+TC3 PASS

8. Forbidden Actions

• ❌ Any * operator in RTL
• ❌ Mutating Lane A' rtl/holo_noc_1cycle.sv from feat(a-prime): holo-noc-1cycle inter-die NoC (P4 falsification) · L-DPC24 Lane A' #13
• ❌ Python or bash in committed code
• ❌ Admin-merging this PR (parent decides)
• ❌ Claiming PASS without conclusion=SUCCESS from CI

9. References

Ref	Link
Lane A' base	tt-trinity-holo#13 at 78362042
Lane W BitROM	tt-trinity-holo#14
Lane V Platinum LUT PE	tt-trinity-max-true#13
Lane X 6-op alphabet	t27#637 at 5758b53c
Algebraic anchor φ²+φ⁻²=3	DOI 10.5281/zenodo.19227877
ASP-DAC 2026 NoC scale-out	arXiv 2511.21910
ONE SHOT parent	trinity-fpga#104
Штаб canonical	trios#834

10. Battle Cry

φ² + φ⁻² = 3 · 4× mesh scale-out · 2×2 holo · NEVER STOP · LANG→SI · DOI 10.5281/zenodo.19227877

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Refs #104